

Command Reference2.  FPGA Express Shell Commands      create_chip


_N_A_M_E
          create_chip    Create an implementation targeted to a
                         chip


SYNTAX
          string create_chip [-arch _a_r_c_h__n_a_m_e]
                 [-target _t_a_r_g_e_t__n_a_m_e] [-device _d_e_v_i_c_e__n_a_m_e]
                 [-speed _d_e_v_i_c_e__s_p_e_e_d] [-frequency _M_H_z] [-module]
                 [-keep_pads] [-library _l_i_b_r_a_r_y__n_a_m_e]
                 [-area_only] [-quick_mode] [-preserve] [-
                 eliminate]
                 [-rmdup_cells] [-progress]
                 -name _c_h_i_p__n_a_m_e
                 _R_o_o_t__d_e_s_i_g_n

         string    _a_r_c_h__n_a_m_e
         string    _t_a_r_g_e_t__n_a_m_e
         string    _d_e_v_i_c_e__n_a_m_e
         string    _d_e_v_i_c_e__s_p_e_e_d
         int  _M_H_z
         string    _c_h_i_p__n_a_m_e
         string    _l_i_b_r_a_r_y__n_a_m_e
         string    _r_o_o_t__d_e_s_i_g_n


ARGUMENTS
          -arch _s_t_r_i_n_g   This argument is ignored. Only one
                         architecutre per entity is allowed in
                         the source files added to the project.
                         Multiple architectures for the same
                         entity must be split into several files,
                         and only the file containing the
                         required architecture should be included
                         in the project.


          -target _s_t_r_i_n_g FPGA target family (see list_target).


          -device _s_t_r_i_n_g Target device.


          -speed _s_t_r_i_n_g  Target device speed grade.


          -frequency _i_n_t_e_g_e_r
                         Target clock frequency (MHz).


          -module        Treat the chip as a module (do not
                         insert I/O).


v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1


create_chip     2.  FPGA Express Shell Commands Command Reference


          -keep_pads     Keep all existing pad cells.  Without
                         this option, all pad cells will be
                         destroyed and pad mapping will be
                         performed on all I/O ports.


          -library _s_t_r_i_n_g
                         Library name.  Defaults to "WORK"


          -area_only     Optimize for area only


          -quick_mode    Quick optimization (low effort)


          -preserve      Preserve hierarchy during optimization.
                         This option is set by default.

          -eliminate     Eliminate hierarchy during optimization.
                         FPGA Express
                          implements "permeable" hierarchy
                         preservation.  Dead logic or inverter
                         pushing may modify user-defined
                         hierarchical boundaries.


          -rmdup_cells   Remove duplicate cells during
                         optimization. For example, duplicate
                         flip-flops and latches are not removed
                         by default.


          -progress      Enable the progress report.  If enabled,
                         progress messages will be displayed
                         while the optimization is running.


          -name _s_t_r_i_n_g   Chip name.  The name of the chip that
                         uniquely identifies that chip and can
                         later be used to reference the chip in
                         other commands.


          _r_o_o_t__d_e_s_i_g_n    Root design.  Note that if the root
                         design is a VHDL entity with several
                         architectures, the specific architecture
                         should be specified using the "-_a_r_c_h"
                         option.


2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0


Command Reference2.  FPGA Express Shell Commands      create_chip


DESCRIPTION
          create_chip creates a chip.  A chip is a hierarchically
          linked design that can later on be optimized and
          exported.  The process involves linking the designs
          hierarchically which may in turn invoke HDL elaboration
          to synthesize designs using context specific
          information.


EXAMPLES
          fe_shell > create_project -dir . fesproj
          fe_shell > add_file prep4.vhd
          fe_shell > analyze_file
          fe_shell > create_chip -target VIRTEX -name p_v prep4
          fe_shell > current_chip -name p_v
          fe_shell > optimize_chip -name prep4_opt
          fe_shell > export_chip
          fe_shell > quit


v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-3