Command Reference2.  FPGA Express Shell Commands      export_chip



_N_A_M_E
          export_chip    Export a chip


SYNTAX
          string export_chip [-dir _e_x_p_o_r_t__d_i_r]
                 [-root _r_o_o_t__p_r_e_f_i_x] [-no_timing_constraint] [-
                 timing_constraint] [-simulation _s_i_m_u_l_a_t_i_o_n__t_y_p_e]
                 [-bus_style _b_u_s__s_t_y_l_e__e_x_p_r_e_s_s_i_o_n] [-primitive]
                 [-db] [-progress]

         string    _e_x_p_o_r_t__d_i_r
         string    _r_o_o_t__p_r_e_f_i_x
         string    _s_i_m_u_l_a_t_i_o_n__t_y_p_e
         string    _b_u_s__s_t_y_l_e__e_x_p_r_e_s_s_i_o_n


ARGUMENTS
          -dir _e_x_p_o_r_t__d_i_r
                         Export directory.  This provides a one-
                         time-only override of the _c_h_i_p _e_x_p_o_r_t
                         _d_i_r_e_c_t_o_r_y which is set by the
                         set_chip_export_directory.


          -root _r_o_o_t__p_r_e_f_i_x
                         Root of filenames to be exported.  Some
                         technologies allow the user to set a
                         filename prefix.



          -no_timing_constraint
                         Do not export timing constraints.


          -timing_constraint
                         Export timing constraints.


          -simulation _s_i_m_u_l_a_t_i_o_n__t_y_p_e
                         Export functional simulation net list
                         (VHDL, VERILOG, or none).


          -bus_style _b_u_s__s_t_y_l_e__e_x_p_r_e_s_s_i_o_n
                         Specify bus naming style.  Check with
                         Synopsys or FPGA vendor Application
                         Engineering before using this option.


          -primitive     Export functional simulation primitives.



v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1






export_chip     2.  FPGA Express Shell Commands Command Reference



                         Selecting this option creates a
                         "complete" simulation model which
                         includes functional simulation
                         descriptions for all used FPGA vendor
                         primitives.  If this option is not
                         selected, the simulator must find the
                         FPGA primitive library in order to
                         simulate.


          -db            Exports two Synopsys DB files for the
                         current chip.  The first DB file
                         contains the design hiearchy for the
                         chip.  The second DB file contains the
                         technology library primitives that are
                         used in the design DB file.  Technology
                         primitives contain both timing and
                         functional information, however, it is
                         not recommended that they be used for
                         technology mapping.  Also, more accurate
                         timing models for the primitives are
                         usually available from FPGA vendors.


          -progress      Enable the progress report



DESCRIPTION
          Writes out the net list for the chip.  This command
          also writes out a simulation model (in either VHDL or
          Verilog), and timing constraints as well as Synopsys DB
          files. This command is only valid for an optimized
          chip.


EXAMPLES
          fe_shell > create_project -dir . fesproj
          fe_shell > add_file prep4.vhd
          fe_shell > analyze_file
          fe_shell > create_chip -target VIRTEX -name p_v prep4
          fe_shell > current_chip -name p_v
          fe_shell > optimize_chip -name prep4_opt
          fe_shell > export_chip
          fe_shell > quit



SEE ALSO
          set_chip_export_directory (2).





2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0