Command Reference2. FPGA Express Shell Commands list_message _N_A_M_E list_message List messages about chips and files SYNTAX string list_message [-file _s_t_r_i_n_g] [-chip _s_t_r_i_n_g] [-no_error] [-no_warning] [- no_message] [-attr] string _s_t_r_i_n_g string _s_t_r_i_n_g ARGUMENTS -file _s_t_r_i_n_g File name (e.g., *.vhd) List all messages received during the processing of file _s_t_r_i_n_g. -chip _s_t_r_i_n_g Chip name (e.g., mychip*) List all messages received during the processing of chip _s_t_r_i_n_g. -no_error Do not list error messages. By default, this command lists all messages. This option prevents error messages from being listed. -no_warning Do not list warning messages. By default, this command lists all messages. This option prevents warning messages from being listed. -no_message Do not list informational messages. By default, this command lists all messages. This option prevents informational messages from being listed. -attr List message attributes. This option lists the various messages received so far along with their attributes. Attributes include the message code, message type (warning,error, etc.), and a brief explanation of the message, if available. v3.0 Synopsys Inc. 1988-1998. All rights reserved. 2-1 list_message 2. FPGA Express Shell Commands Command Reference DESCRIPTION This command is used to list all the messages received during the analysis of files and the optimization of chips. EXAMPLES fe_shell > analyze_file Warning: Parameter range specification is only meaningful to synthesis. Different result may exist from simulations near symbol "]" on line 115 in file design1.v. (VE-122) fe_shell > list_message fe_shell > list_message -file * Warning: Parameter range specification is only meaningful to synthesis. Different result may exist from simulations near symbol "]" on line 115 in file design1.v. (VE-122) fe_shell > list_message -no_warning fe_shell > list_message -file * -attr ====== FILE: design1.v Code: VE-122 Type: WARNING File: design1.v Line: 115 Source: /serverx/fpga_project/design1.v: Explanation: Warning: Parameter range specification is only meaningful to synthesis. Different result may exist from simulations near symbol "]" on line 115 in file design1.v. (VE-122) 2-2 Synopsys Inc. 1988-1998. All rights reserved. v3.0