Command Reference2. FPGA Express Shell Commands object _N_A_M_E object Objects in FPGA Express DESCRIPTION The objects defined by the FPGA Express data models are the following: _f_i_l_e A file is a reference to an HDL source file. _d_e_s_i_g_n A design object is a reference to an HDL design. HDL designs are contained in an HDL library. _m_o_d_u_l_e A module is an instance of an HDL design that is not the top-level design of an implementation hierarchy. A module has a boundary defined by its ports. Module boundaries can be preserved or eliminated during optimization. _p_o_r_t A port specifies an input and/or output signal interface for a chip or module. _p_a_d is another term for a port. _c_e_l_l A cell is an instance of a primitive element in the target technology. _p_i_n A pin specifies an input and/or output signal interface for a cell. _n_e_t A net is an object that represents the electrical connection for a set of pins or ports. _l_i_b_r_a_r_y A library is a container for designs. _c_h_i_p A chip is an implementation of a design and its hierarchical components. The implementation may either be pre- optimized or optimized. v3.0 Synopsys Inc. 1988-1998. All rights reserved. 2-1 object 2. FPGA Express Shell Commands Command Reference _p_r_o_j_e_c_t A project is an object that contains files, chips and libraries. It also defines special variables that are used by various commands in fe_shell. These variables have the _p_r_o_j prefix. FPGA Express creates a directory (folder) and project file when a project is created. _c_l_o_c_k A clock is a net having a periodic behavior. In a synchronous circuit, clocks are used to synchronize the propagation of data signals controlling a sequential element. FPGA Express automatically analyzes a the circuit for clocks. The waveform for the clocks must be specified by the user using the set_clock command. _t_i_m_i_n_g _g_r_o_u_p A timing group is composed of cells with common timing requirements. A timing group is distinguished by cell type (flip-flop, latch), active clock edge or gate level (rising, falling, high, low), and clock or gate signal. Timing groups are automatically determined by FPGA Express . Users may create timing groups called subgroups which contain cells that are a subset of an existing timing group. _p_a_t_h _g_r_o_u_p A path group or timing path is the set of combinational paths from a timing group (called starting group) to another timing group (called ending group). Path groups are automatically determined by FPGA Express . Users may create path groups called subpaths whose starting and ending timing groups are subgroups. _t_a_r_g_e_t A target is a name of an FPGA family of devices. _d_e_v_i_c_e A device or part name identifies a particular package for a target. 2-2 Synopsys Inc. 1988-1998. All rights reserved. v3.0 Command Reference2. FPGA Express Shell Commands object _s_p_e_e_d The speed identifies the speed grade for a particular device and target. OBJECT NAMING Objects created by the user using an fe_shell command are named by the user. Objects in the design hierarchy or automatically generated by FPGA Express follow certain naming conventions. These conventions must be used when specifying objects for operations. Net list objects such as cell, pin, port, and module are specified using pathnames. A pathname always starts with the hierarchy separator character '/' followed by the name of a chip. If the '/' character is part of the object name and not a separator, the '/' character must be escaped using the '' character. See the section on BACKSLASH SUBSTITION for more details. A timing group has the form "(_c_l_o_c_k__t_y_p_e, _c_l_o_c_k__n_e_t)". _c_l_o_c_k__t_y_p_e is one of RC,FC,HL,LL that represents the active clock edge or gate level rising, falling, high, low, respectively. _c_l_o_c_k__n_e_t is the name of a net in the design which FPGA Express has determined to be a clock signal. Timing subgroups can have arbitrary names subject to some character usage limitations. A path group has the form "_s_t_a_r_t__g_r_o_u_p:_e_n_d__g_r_o_u_p". _s_t_a_r_t__g_r_o_u_p and _e_n_d__g_r_o_u_p are the names of the starting and ending timing groups. References to file system objects can be different depending on the operating system platform as well as the type of command shell. The main difference lies in the directory separator character. It is recommended that the '/' character always be used in fe_shell. The '' character is supported as a directory separator, however, it must be escaped when used as an fe_shell argument (see EXAMPLES). Target, device, and speed names depend on the FPGA family. However, the names that are returned by the get_target, get_device, and get_speed commands are the only valid identifiers for commands that accept this information such as the create_chip command. PATH GLOB AND REGULAR EXPRESSIONS Many of the fe_shell commands can accept either a pathname glob or a regular expression for an object pathname. A pathnme glob is pathname expressed in the v3.0 Synopsys Inc. 1988-1998. All rights reserved. 2-3 object 2. FPGA Express Shell Commands Command Reference "glob" pattern style so that more than one object may be matched. Glob-style matching is easier to learn and use than regular expressions, but it works well only for simple cases. For a glob pattern to match, each character of the pattern must be the same as the corresponding character of the string except that a few pattern characters are interpreted specially. * Matches any sequence of zero or more characters. ? Matches any single character. [_c_h_a_r_s] Matches any single character in _c_h_a_r_s. If _c_h_a_r_s contains a sequence of the form _a-_b, any character between a and b, inclusive will match. .XX "object: options; Matches any single character _x. This provides a way to void special interpretation for any of the special glob characters. Regular expressions are more complex than glob-style patterns but more powerful. It is beyond the scope of this document to fully describe the syntax of regular expressions. The user is referred to the regexp UNIX man page. BACKSLASH SUBSTITUTION Many characters have special meaning in Tcl. In order to use these characters in string expressions, the backslash character must be used before the special character. fe_shell also uses backslash characters to allow special characters in the names of its objects. Therefore, the backslash character itself must be sometimes be preserved in the arguments of an fe_shell command. 2-4 Synopsys Inc. 1988-1998. All rights reserved. v3.0 Command Reference2. FPGA Express Shell Commands object Many fe_shell commands requires lists of object names. A Tcl list is represented as strings with a particular structure which allows the user to enter a string value where a list is expected. This usage will work, but backslash substitution becomes somewhat complex. A few following rules can be followed when escaping a character with a backslash: 1. Four backslashes are required when entering a string in place of a list. 2. If the string is enclosed in braces, two backslashes are required. For example, the following report_timing are equivalent: fe_shell > set pin_list [get_pin /*/U2*<1>/C] {/AM2910-Optimized/U2/OUTPUT_reg<1>} fe_shell > report_timing $pin_list fe_shell > report_timing /AM2910- Optimized/U2\\/OUTPUT_reg<1>/C fe_shell > report_timing {/AM2910- Optimized/U2\/OUTPUT_reg<1>/C} EXAMPLES file fe_shell > add_file /users/me/designs/am2910.vhd fe_shell > add_file ../designs/am2910.v fe_shell > add_file d:/designs/am2910.v fe_shell > add_file d:\designs\am2910.v design fe_shell > create_chip -name chip1 AM2910 module fe_shell > set_module_hierarchy preserve /AM2910/U1 fe_shell > set_module_primitive preserve /AM2910/U* /* pathname glob */ fe_shell > get_module /*/* /* pathname glob */ port fe_shell > set_pad_register TRUE /AM2910/D<1> fe_shell > set_pad_register /AM2910/* fe_shell > get_port /*/* cell fe_shell > create_subpath -from_name my_from -to_name my_to -from_list /AM2910/U1/C339 -to_list /AM2910/U1/C340 -maxd 50 (RC,CLOCK):(RC,CLOCK) v3.0 Synopsys Inc. 1988-1998. All rights reserved. 2-5 object 2. FPGA Express Shell Commands Command Reference fe_shell > get_cell /*/*/* pin fe_shell > set_disable_timing /AM2910- Optimized/C1009/I fe_shell > get_pin /AM2910-Optimized/C1009/* library fe_shell > create_library -name my_library fe_shell > list_design -library my_library fe_shell > get_design my_library fe_shell > report_library WORK chip fe_shell > create_chip -name my_chip AM2910 fe_shell > get_chip -regexp my_.* fe_shell > current_chip my_chip chip fe_shell > create_chip -name my_chip AM2910 fe_shell > get_chip my_* /* glob style */ fe_shell > get_chip -regexp my_.* /* regular expression style */ fe_shell > current_chip my_chip project fe_shell > create_project my_project fe_shell > open_project my_project/ fe_shell > open_project my_project/my_project.exp /* equivalent */ clock fe_shell > set_clock -period 50 -rise 25 -fall 50 CLOCK path group fe_shell > set_max_delay -path_group (RC,CLOCK):(RC,CLOCK) 50 fe_shell > report_timing -path_group (I):(RC,CLOCK) SEE ALSO fe_shell (1) 2-6 Synopsys Inc. 1988-1998. All rights reserved. v3.0