Command Reference2.  FPGA Express Shell Commandsset_chip_retiming



_N_A_M_E
          set_chip_retiming
                         Enable retiming optimization on a chip


SYNTAX
          string set_chip_retiming [-_e_n_a_b_l_e | -_d_i_s_a_b_l_e]



ARGUMENTS
          -_e_n_a_b_l_e        Enable retiming optimization.

          -_d_i_s_a_b_l_e       Disable retiming optimization.



DESCRIPTION
          Selecting the -_e_n_a_b_l_e option enables retiming
          optimization on the current chip. When the chip is
          optimized with retiming enabled, FPGA Compiler II will
          attempt to equalize the delay of all paths between
          registers driven by a common clock.  This equalization
          generally reduces the worst-case path between
          registers, thus improving the clock period.

          A common use of retiming is to produce optimal pipeline
          stages.  The user describes the desired combinational
          behavior, and "stacks up" additional registers at the
          inputs of the function in the HDL description.  Each
          input should have the same number of registers; equal
          to the number of pipeline stages the user wants in the
          end.  Ordinary synthesis at this point would produce a
          long clock period due to the implementation of the
          combinational behavior in a single clump of logic, all
          operating in one clock cycle.  Retiming moves the input
          registers into the combinational logic; the retimed
          function outputs behave identically to the original
          outputs, but the redistributed sections of
          combinational logic now have shorter delays, thus
          reducing the clock period.

          Note that the FPGA Compiler II retiming algorithm moves
          registers "forward" more easily than "backward".
          Registers without set or reset can be moved in either
          direction, but registers with set or reset can only be
          moved forward.

          Due to the nature of the retiming algorithm, the final
          number of registers may be different than the initial
          number of registers.  This can make simulation or other
          verification techniques fail.



v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1






set_chip_retiming2.  FPGA Express Shell CommandsCommand Reference



          Selecting the -_d_i_s_a_b_l_e option disables the retiming
          optimization on the current chip.

          The current chip must be defined by using the command
          current_chip before executing this command, otherwise
          an error will be reported.

          The current chip must be "flat" -- it cannot have it's
          hierarchy preserved, otherwise an error will be
          reported.

          The set_chip_retiming command must be issued on an
          unoptimized chip -- prior to issuing the optimize_chip
          command.

EXAMPLES
          Enable retiming optimization on the chip "mychip1".

          fe_shell > current_chip mychip1
          fe_shell > set_chip_retiming -enable


          Disable retiming optimization on the chip "mychip1".

          fe_shell > current_chip mychip1
          fe_shell > set_chip_retiming -disable


SEE ALSO
          current_chip(2), set_chip_hierarchy(2)

























2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0