

Command Reference2.  FPGA Express Shell Commands set_pad_register


_N_A_M_E
          set_pad_register
                         Set pad register optimization.


SYNTAX
          string set_pad_register _P_a_d _r_e_g_i_s_t_e_r _o_p_t_i_m_i_z_a_t_i_o_n _v_a_l_u_e
                 _p_o_r_t _l_i_s_t

         string  _P_a_d _r_e_g_i_s_t_e_r _o_p_t_i_m_i_z_a_t_i_o_n _v_a_l_u_e
         list    _p_o_r_t _l_i_s_t


ARGUMENTS
          _P_a_d _r_e_g_i_s_t_e_r   Pad register optimization option
                         "pad_register_optimization_value"
                         indicates the pad registor value which
                         is assigned to each of the ports in the
                         port_list.
                         Register inference allows coding designs
                         independent of technology, so no
                         register changes are ever needed.
                         I/O register constraints apply to Altera
                         and Xilinx technology only.


          _p_o_r_t _l_i_s_t      List of ports "port_list" is a list of
                         ports, to which the pad register value
                         is to be assigned which is residing in
                         the parameter
                         "pad_register_optimization_value". %


DESCRIPTION
          "set_pad_register" sets the pad resistance value for
          the current chip. The first argument
          "pad_register_optimization_value" specifies the pad
          register type. The second argument "port_list" is a
          list of ports to apply to property to.
          On execution the command returns an integer, where 0
          indicates success, whereas a 1 being returned indicates
          failure.
          Each port has with it a valid list of pad register
          values that can be assigned to it. If the value to be
          assigned is not one among the valid ones, then an error
          is reported, in addition a list of the valid values
          permitted is also displayed.


EXAMPLES
          fe_shell > create_project -dir . fesproj


v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1


set_pad_register2.  FPGA Express Shell Commands Command Reference


          fe_shell > add_file prep1.vhd
          fe_shell > analyze_file
          fe_shell > create_chip -target VIRTEX
           -name part_name prep1
          fe_shell > set_pad_register TRUE /AM2910/D<0>


SEE ALSO
          set_pad_buffer,set_pad_dir, set_pad_resistance,
          set_pad_slew_rate (2)


2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0