Command Reference2.  FPGA Express Shell Commandsset_pad_reg_delay



_N_A_M_E
          set_pad_reg_delay
                         Set pad register delay.


SYNTAX
          string set_pad_reg_delay _I_n_p_u_t _d_e_l_a_y _b_u_f_f_e_r _n_a_m_e
                 _p_o_r_t _l_i_s_t

         string    _I_n_p_u_t _d_e_l_a_y _b_u_f_f_e_r _n_a_m_e
         list      _p_o_r_t _l_i_s_t


ARGUMENTS
          _I_n_p_u_t _d_e_l_a_y    Input pad register delay buffer for pad
                         "Input_delay_buffer_name" specifies the
                         delay which is to be assigned as the pad
                         register delay to each of the ports in
                         the port_list.
                         The use of an input delay reduces the
                         hold time requirement for an input
                         transition. Input register delay
                         constraints apply to Xilinx and Lucent
                         technologies only.
                         The input register delay is the setup
                         time for registers mapped to input pads
                         (XC4000E) or driven directly by input
                         ports (XC5200). In the Xilinx XC4000E
                         family, INFF and INLAT input pads have a
                         control that can increase or decrease
                         the setup time requirement for the INFF
                         and INLAT cells that may be inserted. In
                         the Xilinx XC5200 family, the input pad
                         does not contain a register, but if the
                         input pad drives a flip-flop or latch,
                         the setup time to that register can be
                         increased or decreased.


          _p_o_r_t _l_i_s_t      List of ports "port_list" is a list of
                         ports. Each of the ports in the
                         port_list are assigned the pad register
                         delay.



DESCRIPTION
          "set_pad_reg_delay" sets the pad register delay value
          for the current chip. The first argument
          "Input_delay_buffer_name" specifies the pad register
          delay type. The second argument "port_list" is a list
          of ports to apply the property to. The command on



v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1






set_pad_reg_delay2.  FPGA Express Shell CommandsCommand Reference



          execution returns an integer, a 0 on success, whereas a
          1 on failure.
          Each port has with it a valid list of register delays
          that can be assigned to it. If the value to be assigned
          is not one among the valid ones, then an error is
          reported. In addition a list of the valid values
          permitted is also displayed.


EXAMPLES
          fe_shell > create_project -dir . fesproj
          fe_shell > add_file prep4.vhd
          fe_shell > analyze_file
          fe_shell > create_chip -target VIRTEX -name p_v prep4
          fe_shell > set_pad_reg_delay SLOW /AM2910/D<5>


SEE ALSO
          set_pad_buffer,set_pad_dir, set_pad_register,
          set_pad_slew_rate. (2)



































2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0