

Command Reference  2.  FPGA Express Shell Commandsset_module_rmdup_cells


_N_A_M_E
          set_module_rmdup_cells
                         Enables/Disables the remove duplicate
                         cells optimization on a module or list
                         of modules.


SYNTAX
          string set_module_rmdup_cells
                 [_E_n_a_b_l_e | _D_i_s_a_b_l_e | _I_n_h_e_r_i_t | <_d_e_f_a_u_l_t>]
                 _m_o_d_u_l_e-_l_i_s_t


         string    _E_n_a_b_l_e, _D_i_s_a_b_l_e, _I_n_h_e_r_i_t, <_d_e_f_a_u_l_t>
         list _m_o_d_u_l_e _l_i_s_t


ARGUMENTS
          _o_p_t-_v_a_l_u_e_s     _E_n_a_b_l_e, _D_i_s_a_b_l_e, _I_n_h_e_r_i_t, <_d_e_f_a_u_l_t>


          _m_o_d_u_l_e _l_i_s_t    List of modules


DESCRIPTION
          This command is used to enable or disable on a module
          or list of modules the optimization which removes
          duplicate cells.  The remove _d_u_p_l_i_c_a_t_e _c_e_l_l_s
          _o_p_t_i_m_i_z_a_t_i_o_n step recognizes duplicate registers and
          merges them into a single register.

          A pair of cells are _d_u_p_l_i_c_a_t_e_s if the two cells are of
          the same type and function (i.e. DFF D-flip-flop) and
          each of the corresponding inputs to the pair of cells
          are connected to the identical sets of input nets.  If
          a pair of duplicate cells is identified, one cell is
          deleted and the output nets of the deleted cell are
          merged with the corresponding output nets of the
          remaining cell.  If duplicate cells are discovered when
          optimize_chip is executed, a message will be generated
          for each cell which has been deleted.  Note that this
          optimization will remove registers from your design
          which may have undesirable effects (i.e. may cause
          simulation issues, flip-flops may not be able to be
          mapped to a pad).

          The optimization values that can be set on a module
          are:

          Enable         Enables the optimization in this module
                         and its sub-modules.


v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1


set_module_rmdup_cel2l.s FPGA Express Shell Commands   Command Reference


          Disable        Disable the optimization in this module
                         and its sub-modules.

          Inherit        Inherit the value from the the module's
                         parent.

          <default>      Reset the value to the default value.
                         This will typically be equivalent to
                         setting the value to _I_n_h_e_r_i_t.

          Setting a value of Enable or Disable on a module not
          only controls the optimization on the specified module
          but also defines the default value for all submodules
          in the hierarchy below this module.  Any module which
          has the value Inherit will inherit its value from the
          parent module in the hierarchy of the chip. If the
          parent module's value is Enable or Disable then the
          module's value will be that of the parent.  If the
          parent module value is Inherit then the value is taken
          from the parent module's parent. If all of the modules
          from the specified module to the top module in the chip
          hierarchy have the value Inherit, then the default
          value for the chip is used. The default value for the
          chip is set when the chip is created, see create_chip
          for more information.

          This command requires that the current chip is defined,
          otherwise an error message is reported.

          Currently the _r_e_m_o_v_e _d_u_p_l_i_c_a_t_e _c_e_l_l_s optimization only
          considers flip-flop and latch cells in the chip.


EXAMPLES
          fe_shell > current_chip mychip
          fe_shell > set_module_rmdup_cells Enable top/submod1


SEE ALSO
          current_chip(2), create_chip(2), optimize_chip(2)


2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0