Command Reference2.  FPGA Express Shell Commands set_module_block



_N_A_M_E
          set_module_block
                         Specify block option for a module


SYNTAX
          string set_module_block {_t_r_u_e | _f_a_l_s_e}
                                   _m_o_d_u_l_e _l_i_s_t

          string    _t_r_u_e, _f_a_l_s_e
          list _m_o_d_u_l_e _l_i_s_t


ARGUMENTS
          _t_r_u_e           This option specifies that the modules
                         in the module list are the root modules
                         of a block.

          _f_a_l_s_e          This option specifies that the modules
                         in the module list are not the root
                         modules of a block.

          _m_o_d_u_l_e _l_i_s_t    List of modules to apply the value of
                         true or false to.



DESCRIPTION
          Use this command to define the blocks of a chip by
          specifying the root or top modules of each block.
          Defining two or more blocks in a chip enables
          incremental implementation and optimization of the
          blocks. See chip_update(2) for more details on the
          incremental synthesis behavior.

          The option value specified must either be true or
          false, otherwise an error will be reported as follows:

          Error: Invalid block option - must be either 'true' or
          'false'

          The top-level module  of the chip is by definition a
          block root and therefore its value cannot be modified
          from its value of "true". All user defined modules can
          be either designated a block root (_t_r_u_e) or not a block
          root (_f_a_l_s_e). The block root can only be designated on
          user modules. Attempting to set it on a non-user
          module, such as a primitive, or the top-level module of
          the chip will result in the following error message:

          Error: Cannot set block option on module 'AND'




v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1






set_module_block2.  FPGA Express Shell Commands Command Reference



          Blocks may only be designated on the modules of a chip
          whose target technology is currently supporting the
          incremental synthesis behavior.  Attempting to use this
          command on an architecture which is not supported will
          result in the following error message:

          Error: block assignments are not supported for the
          target technology of this chip


Definitions
          A _b_l_o_c_k is the set of modules that form a sub-tree of
          modules in the chip.  The top or root module of this
          tree is called the block root.  The set of modules of a
          block includes the block root and all modules in the
          largest tree of the hierarchy rooted at the block root
          that does not include another block root.  Below is an
          example of a chip hierarchy containing modules top, a,
          b, c, d, e, f:

              top
              |  \
              a   b
              |\  |\
              c d e f

          By definition _t_o_p is a block root. If in addition to
          _t_o_p, that _a, _e are designated as block roots, then the
          blocks of this chip would be the following:

              {top, b, f}
              {a, c, d}
              {e}

          The optimizer uses the block definitions to restrict
          the optimizations across the boundaries of a block such
          that the logical behavior as viewed from the I/O's of
          the block are preserved.  For example boundary
          optimizations (constant propagation, moving inverters
          accross hierarchical boundaries) are restricted within
          a block but are disabled across block boundaries. This
          feature is used to enable incremental updates of the
          blocks of the chip rather than a complete re-
          optimization of all modules of the chip. See
          chip_update(2) for more details.


EXAMPLES
          In this example, the chip TOP has 3 sub-modules,
          /TOP/block1, /TOP/block2, /TOP/x. To specify that the
          chip be partitioned into 3 blocks, one block containing
          just module /TOP/block1, another block containing just



2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0






Command Reference2.  FPGA Express Shell Commands set_module_block



          module /TOP/block2 and the third block containing the
          modules /TOP and /TOP/x, the following command could be
          used:

          fe_shell > set_module_block /TOP/block1 /TOP/block2

          Note that it is not necessary to define the block root
          for the block containing TOP since the top-level module
          of the chip is always a block root.


SEE ALSO
          optimize_chip(2), update_chip(2), get_module(2)










































v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-3