

Command Reference2.  FPGA Express Shell Commandstranslate_dc_script


_N_A_M_E
          translate_dc_script
                         Translates a DC script in a top-down-
                         synthesis FST script


SYNTAX
          translate_dc_script -input_script _d_c__s_h_e_l_l__s_c_r_i_p_t
                 -output_script _f_e__s_h_e_l_l__s_c_r_i_p_t
                 [-help] [-top top_module] [-family family]
                 [-device device] [-speed speed_grade] [-clock
                 freq]
                 [-pads yes|no] [-hierarchy yes|no]
                 [-objective area|speed] [-effort low|high]

         string    _t_o_p__m_o_d_u_l_e
         string    _f_a_m
         string    _d_e_v
         string    _s_p_e_e_d__g_r_a_d_e
         integer   _f_r_e_q


ARGUMENTS
          -help          help message

          -file _d_c__s_h_e_l_l__s_c_r_i_p_t
                         Input dc_shell script

          -output_script fe_shell_script Output fe_shell
                          script.

          -top _s_t_r_i_n_g    top module/entity name

          -family _s_t_r_i_n_g target family

          -device _s_t_r_i_n_g target device

          -speed _s_t_r_i_n_g  target speed grade

          -clock _i_n_t_e_g_e_r global glock frequency

          -pads _y_e_s|_n_o   pad insertion

          -hierarchy _y_e_s|_n_o
                         hierarchical synthesis

          -objective _a_r_e_a|_s_p_e_e_d
                         optimization goal

          -effort _l_o_w|_h_i_g_h
                         CPU effort


v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1


translate_dc_script2.  FPGA Express Shell Commands Command Reference


DESCRIPTION
          This command translates a DC-script into a FST script
          for FPGA Compiler II.  The recommended synthesis
          methodology for FPGA Compiler II is a top-down, flat,
          full-chip synthesis.  Regardless of the methodology
          used in the DC script, translate_dc_script extracts
          relevant information from the DC-script, and creates a
          top-down-synthesis FST script.

          The goal is to provide a basic FST template that the
          user can modify.  The FST script is commented to make
          the understanding and future modifications easier.

          Optional parameters, if used, will take precedence over
          the information found in the DC-script.  For the list
          of available parts, use following FST commands:
          get_target, get_device, get_speed


EXAMPLES
          This example translates a DC script (run.scr) in a FST
          script (run.fst) and overrides the target
          device/speed-grade, the global clock frequency
          constraint, and the synthesis objective.

               fe_shell > translate_dc_script run.scr run.fst
                 -family VIRTEX -device V50PQ240 -speed -4
                 -objective area -clock 50


SEE ALSO
          get_target(2),get_device(2),get_speed(2)


2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0