Command Reference2.  FPGA Express Shell Commands      update_file



_N_A_M_E
          update_file    Update file


SYNTAX
          string update_file [-force]
                 [-progress] [_L_i_s_t _o_f _f_i_l_e_s]

         string    _L_i_s_t _o_f _f_i_l_e_s


ARGUMENTS
          -force         Force update.  Updates the file even if
                         it is already up-to-date.


          -progress      Show progress.  Displays the progress
                         messages while updating the file.


          _L_i_s_t _o_f        Files to be updated (e.g., *.vhd).  List
                         of files to be updated is specified.
                         Single files can also be specified. This
                         is a required argument.



DESCRIPTION
          This command reanalyzes the file specified. It is
          similar to the analyze_file command.

          Analysis of a file is done when it is out of date with
          respect to its source. If force is used, always analyze
          the file.

          For VHDL and Verilog files, the analysis does syntax
          checking and synthesis policy checking and converts the
          source files into intermediate representations ready
          for elaboration.

          For EDIF and XNF , analysis only reads the files into
          the project.



EXAMPLES
          This example analyzes an already analyzed file.

          fe_shell > update_file /tmp/vhdl/test1.vhd

          It can be used to analyze the file which has not been
          analyzed previously.



v3.0      Synopsys Inc. 1988-1998. All rights reserved.       2-1






update_file     2.  FPGA Express Shell Commands Command Reference



          fe_shell > add_file -format Verilog
          /tmp/Verilog/test5.v
          fe_shell > list_files
          VHDL OK /tmp/vhdl/test1.vhd (WORK)
          Verilog Unanalyzed /tmp/verilog/test5.v (WORK)
          fe_shell > update_file /tmp/verilog/test5.v
          fe_shell > list_design -library WORK
          test1_vhd (/tmp/vhdl/test1.vhd) (WORK)
          test5_v  (/tmp/verilog/test5.v) (WORK)


SEE ALSO
          add_file (2), list_files (2), list_design (2),
          open_project (2).









































2-2       Synopsys Inc. 1988-1998. All rights reserved.      v3.0