Command Reference  3.  Attributes and Variables proj_xnfin_bus_style



_N_A_M_E
          proj_xnfin_bus_style


SYNTAX
          _S_t_r_i_n_g proj_xnfin_bus_style = _b_u_s__s_t_y_l_e__e_x_p_r_e_s_s_i_o_n


DESCRIPTION
          This bus style is used for reading XNF net-lists when
          your target technology is Xilinx.

          If you are mixing HDL code with XNF modules, you may
          need to specify how the buses of the design are
          expanded into individual signals because XNF has a wide
          variety of bus styles.

          If FPGA Express cannot determine which individual
          signals in the XNF net-list to map to the bus signals
          defined in the HDL code, you might get a "Failed to
          Link" Error message.

          The most probable XNF format is the default:
                    "%s<%d>"
          This variable only exists when a project is opened or
          created.  To determine the current value of this
          variable, use
               fe_shell > printvar proj_xnfin_bus_style.



























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