FPGA Express, Version 3.4
Release Notes

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This document contains the product release notes for version 3.4 of FPGA Express, your Synopsys programmable logic device (PLD) logic-synthesis solution. This document also includes information about the enhancements and upgrades for two earlier releases, 3.3 and 3.3.1.

Installation information is in a separate document, FPGA Express Installation Guide.

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Other Sources of Information

Other sources of information include

• Altera WWW site--http://www.altera.com
• Synopsys FPGA WWW site--
  http://www.synopsys.com/products/fpga/
• FPGA Express Getting Started (online)
• FPGA Express Installation Guide
• FPGA Compiler II / FPGA Express VHDL Reference Manual (online only)
• FPGA Compiler II / FPGA Express Verilog HDL Reference Manual (online only)
• FPGA Express Online Help and Tutorial
• FPGA Express Online Quick Tour (PC installations only)

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In This Document

This document contains the following sections:

• What is FPGA Express?
• Launching FPGA Express
• Features and Enhancements
• Known Issues and Workarounds
• Improving Quality of Results Using Arithmetic Packages in VHDL
• Product Support

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What is FPGA Express?

FPGA Express is a powerful synthesis tool for leading FPGA and PLD architectures. The OEM version for Altera includes the following features:

• Architecture-specific mapping and optimization for all Altera architectures
• Industry-leading quality of results (QoR)
• Support for industry-standard Verilog and VHDL
• Easy-to-use design flows and graphical user interfaces
• Integrated static timing analysis with TimeTracker
• Vista (visual tools for analysis) including schematic viewing with tight links to TimeTracker
• Tcl-based language for scripting

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Launching FPGA Express

To launch FPGA Express in Windows, go to the Start menu and choose Programs > Synopsys > FPGA Express.

To launch the FPGA Express shell, enter fe_shell in a shell or command window.

For more information, see the FPGA Express Installation Guide.

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Features and Enhancements

The next sections present new features and enhancements for versions 3.4, 3.3.1, and 3.3.

See also Improving Quality of Results Using Arithmetic Packages in VHDL.

New in Version 3.4

The following features were introduced in version 3.4 of FPGA Express.

New Architectures Supported

The ACEX1K, APEX20K60E, and MAX3000 architectures were added in version 3.4 of FPGA Express.

Enhancements to Architecture Support

Version 3.4 of FPGA Express includes improved TimeTracker accuracy for APEX20K and APEX20KE architectures.

Enhancements to Graphical User Interface

Version 3.4 of FPGA Express includes the following enhancements to the Graphical User Interface (GUI):

• The Schematic Viewer now has search capability to locate nets, instances, ports, and modules. Access this feature by choosing View > Find Schematic Object.
• When you select a cell in the Schematic Viewer, that cell is now highlighted in the Paths constraint table of the Constraint Manager for timing analysis.

New in Version 3.3.1

The following features were introduced in version 3.3.1 of FPGA Express:

• Register Duplication
• New Architecture Supported

Register Duplication

Version 3.3.1 of FPGA Express supports register duplication to control register fanout. Register duplication is available for APEX20K and APEX20KE devices.

You can define the maximum fanout either globally or on a register-by-register basis, using either the GUI or the shell.

• In the GUI, use Synthesis > Options > Optimization to set the maximum fanout globally or use the Registers constraint table to set the maximum fanout on a register-by-register basis.
• In the shell, use the set_chip_max_fanout command to set the maximum fanout globally. Use the set_cell_max_fanout command to set the maximum fanout on a register-by-register basis.

For more information about these commands and their options, enter man set_chip_max_fanout or man set_cell_max_fanout at the shell prompt. The command get_register returns a list of all registers.

New Architecture Supported

Version 3.3.1 of FPGA Express adds initial support for the Altera APEX20KE architecture.

New in Version 3.3

The following features were introduced in version 3.3 of FPGA Express:

• Support for "dont_touch"
• Enhancements to Architecture Support

Support for "dont_touch"

With version 3.3 of FPGA Express, you can set a dont_touch attribute on a module, entity, cell, or instance of a design. Setting this attribute prevents optimization of that portion of the design, effectively specifying it as a black box.

By default, the dont_touch attribute is set to false. To change the default in the GUI,

1. Right-click the elaborated implementation, and choose Edit Constraints from the pop-up menu.
2. Select the Modules constraint table and use the Dont Touch column to change the settings for any combination of modules, entities, cells, or instances.

To change the default in the shell, use the following command:

set_module_dont_touch 

For more information about this command and its options, enter the following at the shell prompt:

man set_module_dont_touch

Enhancements to Architecture Support

Version 3.3 of FPGA Express includes improved performance for APEX20K devices.

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Known Issues and Workarounds

Version 3.4 of FPGA Express includes the following known issues and workarounds.

Using Altera MegaWizard Components

Problem: Instantiating components generated by Altera MegaWizard Plug-In Manager and synthesizing them in FPGA Express causes the tool to crash.

Workaround: Instantiate the components generated by Altera MegaWizard Plug-In Manager as black boxes in the design.

• In Verilog, instantiate the MegaWizard-generated component and create an empty module to provide port direction information.
• In VHDL, instantiate the MegaWizard-generated component and provide a component declaration for port direction information.

Synthesize the design without the actual MegaWizard-generated files. FPGA Express treats them as unlinked cells in the netlists.

Place the MegaWizard-generated files in the same directory as the netlists. Use Quartus or MAX+plus II to link the MegaWizard files during place and route.

For more information, see the online application note "Using Altera MegaWizard Components in FPGA Compiler II and FPGA Express."

Turning on Use I/O Reg for APEX20K and APEX20KE Devices

Problem: Turning on Use I/O Reg (in the Ports constraint table) for APEX20K and APEX20KE devices has no effect on synthesis.

Workaround: None. Use I/O Reg is not currently available for APEX20K and APEX20KE devices.

Specifying Multiple License Files Using LM_LICENSE_FILE in Windows NT

Problem: Spaces between license file names in the LM_LICENSE_FILE variable (Start > Settings > Control Panel > System > Environment) causes FPGA Express to crash when launched.

Workaround: Use only the ; (semicolon) character to separate license file names you specify in the LM_LICENSE_FILE variable; remove any spaces between license file names.

VHDL alias Construct

Problem: The VHDL alias construct is not fully supported.

Workaround: Modify your source code. To avoid syntax errors during analysis, include the alias subtype in each alias definition.

For example,

signal a : 	 	 	 std_logic_vector(7 downto 0);

alias top is a(7 downto 4);     	 	 	 	 	 	 	 -- not supported

alias btm :	 	 	 std_logic_vector(3 downto 0) 
           	 	 	 is a(3 downto 0);  	 	 	 	 -- supported

Using export_chip in fe_shell

Problem: The script_chip command generates an export_chip command with a directory path that cannot be read later by the shell itself or the GUI.

Workaround: Before running the scripts that the shell has created, ensure that the directory path for the export_chip command is correct and contains the forward slash (/) rather than the backward slash (\).

Viewing Results in TimeTracker

Problem: The "Review disabled pins" function fails when you view paths in TimeTracker.

Workaround: To enable a pin that has been disabled, close the constraint table, click the right mouse button on the optimized implementation, and select View Results again.

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Improving Quality of Results Using Arithmetic Packages in VHDL

In VHDL designs, you are not required to use arithmetic packages for comparators (<, >, <=, >=, =). However, using arithmetic packages leads to better quality of results in both area and speed because architecture-specific resources are used for the arithmetic operators. Note that you must use arithmetic packages for all operators other than comparators.

To use an arithmetic package for STD_LOGIC vectors, include the following lines before each entity declaration:

• For unsigned operators

  Library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.STD_LOGIC_UNSIGNED.all; 
     -- Arithmetic package for unsigned operators
  

• For signed (2's complement) operators

  Library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.STD_LOGIC_SIGNED.all; 
     -- Arithmetic package for signed operators
  

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Product Support

Altera provides several points of contact for technical support for FPGA Express.

E-Mail Support

Send e-mail to Altera Applications at

sos@altera.com

Telephone Support

Call Altera Applications at

1-800-800-EPLD (United States and Canada)

World Wide Web Site

As an FPGA Express customer, you have access to the Altera World Wide Web site at

http://www.altera.com

The Web site offers technical and general information, including:

Automated assistance
Altera product descriptions and announcements
Descriptions of Altera training and support services
The Altera Technical Support (AtlasSM) database

 

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