// FSM example -encoded one-hot- in Verilog

module shift (clk, rst, in, out);
input clk, rst;
input [2:0] in;
output [2:0] out;
parameter [2:0]
    S0 = 3'b001,
    S1 = 3'b010,
    S2 = 3'b100;

// synopsys state_vector state
reg [2:0] state, next_state ;

always @ (in or state)
begin
    case (state) // synopsys parallel_case full_case
    S0: next_state = S1;
    S1: if (in == 3'b000) next_state = S2;
        else next_state = S1;
    S2: next_state = S0;
    endcase
 end

always @ (posedge clk or posedge rst)
begin
    if (rst) state <= S0;
    else state <= next_state;
end

assign out = state;
endmodule