-- prep1 design

entity prep1 is
    port (CLK,RST,s_l : bit;
	s: bit_vector (1 downto 0);
	d0,d1,d2,d3: bit_vector (7 downto 0);
	q: out bit_vector (7 downto 0));
end prep1;

architecture behavior of prep1 is
   signal reg, shft: bit_vector (7 downto 0);
begin
   process (RST, CLK)
   begin
	if (RST='1') then
	     reg <= x"00";
	     shft <= x"00";
	elsif (CLK='1' and CLK'event) then
	     case s is
		when b"00" => reg <= d0;
		when b"01" => reg <= d1;
		when b"10" => reg <= d2;
		when b"11" => reg <= d3;
	     end case;
	     if s_l = '1' then
		shft <= shft(6 downto 0) & shft(7);
	     else
		shft <= reg;
	     end if;
	end if;
    end process;
  q <= shft;
end behavior;