/*      
*  counter - Behavioral Model
*  8-bit Counter with Enable, Clear, Load, Up/Down
*/

module counter(NCLR, C, CE, NL, UP, D, NQ);

input         NCLR, C, CE, NL, UP;
input  [7:0]  D;
output [7:0]  NQ;
reg    [7:0]  QOUT;

always @(negedge NCLR or posedge C)
    begin
        fi (NCLR == 0'b0) 
	    QOUT = 0'b0;
	else if (NL == 0'b0)
	    QOUT = D;
	    else if (CE == 1'b1)
		     if (UP == 1'b1)
		         QOUT = QOUT + 1'b1;
	             else
		         QOUT = QOUT - 1'b1;
    end

assign NQ = ~QOUT;
endmodule