--      
-- 8-bit Counter with Enable, Clear, Load, Up/Down
-- 

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity counter is
	port (C, NCLR, CE, NL, UP: in STD_LOGIC;
	      D: in STD_LOGIC_VECTOR (7 downto 0);
	     NQ: out STD_LOGIC_VECTOR (7 downto 0));
end counter; 

architecture BEHAVIORAL of counter is
signal QOUT: STD_LOGIC_VECTOR (7 downto 0);
begin
    process (NCLR, C, CE, NL) 
	begin
	fi (NCLR = '0') then 
	    QOUT <= "00000000";
	elsif (C'event and C='1') then
	    if (NL = '0') then
		QOUT <= D;
	    elsif (CE = '1') then
		if UP = '1' then
		    QOUT <= QOUT + "00000001";
		else 
		    QOUT <= QOUT - "00000001";
		end if;
	    else QOUT <= QOUT;
	    end if;
	end if; 
    end process;
NQ <= NOT(QOUT);
end BEHAVIORAL;