--      
-- TUTOR - Top-Level
-- 8-bit Counter with Enable, Clear, Load, Up/Down
-- 

Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity tutor is
	port (CLK, NOTCLR, CLKEN, NOTLD, UPCNT: in STD_LOGIC;
	      DI: in STD_LOGIC_VECTOR (7 downto 0);
	      QO_LO: out STD_LOGIC_VECTOR (7 downto 0));
end tutor; 

architecture structure of tutor is

component counter
	port (C, NCLR, CE, NL, UP: in STD_LOGIC;
	      D: in STD_LOGIC_VECTOR (7 downto 0);
	     NQ: out STD_LOGIC_VECTOR (7 downto 0));
end component;

begin

my_counter: counter
	port map (CLK, NOTCLR, CLKEN, NOTLD, UPCNT, DI, QO_LO);

end structure;