Array Adder

Features

• Parameterized word length and number of input buses

• DADDA tree architecture with optional Final Adder

• Optional pipeline for implementation with Final Adder

• Behavioral simulation model in VHDL and Verilog

Family Support

SX, SX-A, eX, 500K, PA, Axcelerator, ProASIC3/E, Fusion

Description

The Array-Adder implements a Sum-Function over an array of buses:

Sum = [Summation(Data(i))] where i = 0 to Size-1

In applications where designers have to add more than two operands at a time “Carry-Save- Techniques” might be used to build the final Sum. SmartGen makes these techniques available through the Array-Adder core, which is using a Dadda tree algorithm. Usually this algorithm is more compact and faster than using Adder trees consisting of multiple 2-operand adders, especially if the number of operands gets large and/or for large word width.

An example could be the FIR-filter architecture using a “distributed arithmetic” as described in the Application Note from September 1997 Designing FIR Filters with Actel FPGAs. This architecture generates a large number of partial products, which need to be summed. Summing them in an Adder-Tree would both be slow and area-expensive. At the time of writing this document, synthesis tools did not infer Multiple-Operand-Adders. Therefore making use of the Array-Adder in those types of applications might result in a significant gain in both speed and area.

The Array Adder comes with or without Final Adder. The version with Final Adder allows SmartGen to instantiate a pipeline stage between the Dadda-tree and the Final Adder. The output bitwidth for Sum can be calculated using this formula:

OUTWIDTH = log2((m*exp2(n)-1)+1) <= n + log2(m)

The version without Final Adder has two output ports: SumA and SumB, which added together will provide the Final Result. It is

SumA_Width <= SumB_Width <= OUTWIDTH

The differences are at most one bit. This variation of the Array-Adder is particularly useful for an application that would cascade the Array-Adder. In that case only the last stage would need a Final Adder to build the result.