Parameterized word length and FIFO depth
Dual-port synchronous FIFO
Active High/Low enable
Static/ Programmable/No Almost empty/full flags
Full and Empty flags
Axcelerator
Axcelerator provides dedicated blocks of FIFO. They are actually hardwired using the RAM blocks plus some control logic. Each FIFO block has a read port and a write port. Both ports are configurable (to the same size) to any size from 4Kx1 to 128x36; thereby, allowing built-in bus width conversion (see SRAM Port Aspect Ratio table below). Each port is fully synchronous. The FIFO block offers programmable Almost Empty and Almost Full flags as well as Empty and Full flags. The FIFO block may be reset to the empty state.
|
SRAM Port Aspect Ratio |
|
Width |
Depth |
ADDR Bus |
Data Bus |
|
1 |
4096 |
ADDR[11:0] |
DATA[0] |
|
2 |
2048 |
ADDR[10:0] |
DATA[1:0] |
|
4 |
1024 |
ADDR[9:0] |
DATA[3:0] |
|
9 |
512 |
ADDR[8:0] |
DATA[8:0] |
|
18 |
256 |
ADDR[7:0] |
DATA[17:0] |
|
36 |
128 |
ADDR[6:0] |
DATA[35:0] |
Blocks can be cascaded to create larger sizes, up to the capacity of one whole column of RAM blocks. SmartGen performs all the necessary cascading for achieving the desired configuration.
The maximum WIDTH (word length) value is 65,536. The maximum DEPTH (number of words) value is 576.
The write enable (WE) and read enable (RE) signals are active high or low request signals for writing and reading, respectively; you may choose not to use them.
The RCLK and WCLK pins have independent polarity selection.
|
Port Description |
|
Name |
Size |
Type |
Req/Opt |
Function |
|
Data |
Width |
Input |
Req. |
Data Port |
|
WE |
1 |
Input |
Opt. |
Write Enable |
|
WClock |
1 |
Input |
Req. |
Write Clock |
|
Q |
Width |
Output |
Req. |
Q Port |
|
RE |
1 |
Input |
Opt. |
Read Enable |
|
RClock |
1 |
Input |
Req. |
Read Clock |
|
Full |
1 |
Output |
Req. |
Full Flag |
|
Empty |
1 |
Output |
Req. |
Empty Flag |
|
Afval |
1-8 |
Input |
Opt. |
Almost Full, Dynamically programmable |
|
Aeval |
1-8 |
Input |
Opt. |
Almost Empty, Dynamically programmable |
|
AFull |
1-8 |
Output |
Opt. |
Almost Full Flag |
|
AEmpty |
1-8 |
Output |
Opt. |
Almost Empty Flag |
|
Parameter Description |
|
Parameter |
Value |
Function |
|
WIDTH |
Width |
Word length of Data, Q |
|
DEPTH |
Depth |
FIFO Depth |
|
WE_POLARITY |
1 0 2 |
Write Enable Polarity |
|
RE_POLARITY |
1 0 2 |
Read Enable Polarity |
|
WCLK_EDGE |
RISE FALL |
Write Clock Edge |
|
RCLK_EDGE |
RISE FALL |
Read Clock Edge |
|
AEVAL |
Almost Empty Value |
Almost Empty Flag |
|
AFVAL |
Almost Full Value |
Almost Full Flag |
|
DEVICE |
75 150 300 600 1000 |
Target Device, to determine blocks available for cascading |
|
Implementation Parameters |
|
Parameter |
Value |
Description |
|
LPMTYPE |
LPM_FIFO |
Generic Dual-Port FIFO Category |
|
LPM_HINT |
STATIC |
Static AF/AE Flags |
|
DYNAMIC |
Dynamic AF/AE Flags | |
|
NOFLAGS |
No AF/AE Flags |
|
Parameter Rules |
|
Device |
Parameter rules |
|
|
Axcelerator |
WWIDTH |
AEVAL/AFVAL UNITS |
|
000 |
28-W | |
|
001 |
||
|
010 |
||
|
011 |
||
|
100 |
||
|
101 |
||
|
11x |
||
In the Axcelerator FIFO, the AFVAL and AEVAL signals are each eight bits. The step size of the signal varies based on the aspect ratio to which the FIFO blocks are configured.
For example, if the FIFO is configured in the 128X36 aspect ratio, the step size is eight. That means, if a 00000011 is programmed on the AEVAL, the almost empty flag asserts after 3*8 = 24 words are written. The step sizes can be calculated from the above table for other configurations.
SmartGen automatically adjusts the AF and AE thresholds specified by changing them to the nearest step size. A message is also printed in the log file.
Since eight is the least step size for AFVAL and AEVAL, static flag configuration is not supported for widths below eight.
When SmartGen is used to configure the FIFO to a depth that is less than the total available depth, FULL flag will not assert at the depth specified in SmartGen. For example, if FIFO is configured to a 250X18, then SmartGen provides a total depth of 256, which is the closest size. FULL flag will assert at 256. SmartGen prints a message in the log file indicating what configuration it is providing, taking all these details into consideration.
When FIFOs are cascaded deep, the data gets written to multiple FIFO blocks. The FIFO Error flags (AFULL_ERR, AEMPTY_ERR, FULL_ERR, EMPTY_ERR) indicate if one or more of the FIFOs are in a different state than expected. You can ignore them if you wish. These ports get generated only if you are cascading FIFOs wide.