CRC Minicore

Features

• General-purpose Cyclic Redundancy code generator

• Fully synchronous, single-clock operation (greater than 100 MHz for many configurations)

• Parameterized arbitrary polynomial (from 1 up to 64-bit)

• Parameterized data input width

• Parameterized register initialization

• Parameterized bit and byte ordering

• Parameterized bit pattern for CRC output XOR with

Family Support

Axcelerator

Description

The CRC Minicore is a universal Cyclic Redundancy Check (CRC) Polynomial generator that validates data frames and ensures data integrity during data transmission.

To meet different application requirements, the CRC Minicore provides many different configuration parameters. These parameters control data width, a register initialization value, and other CRC output data characteristics.

• Data width specifies the number of bits over which the CRC Minicore generates the CRC value in a single clock cycle. For example, a CRC32 with 8-bit data width performs CRC calculations on 8 bits per clock.  

• Register initialization provides the seed value for CRC generation.

• Additional parameters provide additional flexibility in controlling CRC data characteristics

CRC Variations - There are industry standards for the polynomial value (we will use the variable 'Y' to denote the polynomial value), such as Kermit, CANBus, etc. This option merely allows you to specify which polynomial value you wish to use.

CRC XOROUT - After the calculation of (stream of bits)/(polynomial value) is performed, the remainder (aka CRC) is inserted into the data stream and sent to the receiver.

This CRC value can be inserted in a variety of ways:

• Non-Inverted: CRC result inserted into data stream as-is.

• Inverted: CRC result inserted into data stream with every bit inverted

• 010101: CRC result inserted into data stream with even bits inverted

• 101010: CRC result inserted into data stream with odd bits inverted

Bit Order - In many cases, the CRC input data will be greater than a single bit. This option merely specifies which order the bits are processed. The reason is because some standards require a “reflection” of the bits during transmission (i.e. Reversing the bits), thereby for a byte-wide data, bit 7 or bit 0 could be seen first depending upon the transmission protocol used.

• MSB first: The high order bit is processed first

• LSB first: The low order bit is processed first

Byte Order - The reasoning for this follows above, except it extends it into bytes.  

• MSB First: The high order byte is processed first

• LSB First: The low order byte is processed first

Initial Reg. Value - This is associated with the polynomial you choose, the CRC algorithm uses this value when it starts the algorithm. Review the Standard CRC Generator Parameters table below; each standard contains an initial value. Specify this value according to the standard you have chosen.

• 0000: Initial Register is all 0’s

• FFFF: Initial Register is all F’s

• Dynamic: Initial Register is an input into the generated module of (bit-width) = (the polynomial size). The input name is init_reg.

Run/Shift Control - This option allows the CRC to function as a CRC function AND just a plain serial shifter. By enabling this option, the CRC module will contain an extra 1-bit input pin.  

When the input is high, the CRC function operates as a CRC generator. When the input is low, the CRC is serially shifted to the right.

• No: Run/Shift input pin will not be generated for the module

• Yes: Run/Shift input pin will be generated for the module

For example, the CRC output XOR bit pattern parameter (XOROUT) controls inversion of the CRC value before injecting it into the data stream. Although the CRC Minicore generator provides seven commonly-used CRC polynomials, SmartGen also allows entry of an arbitrary polynomial. The polynomial bit size spans 1 to 64 inclusive..