Parameterized output size (DECODES)
Behavioral simulation model in VHDL and Verilog
ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, eX, 500K, PA, Axcelerator, ProASIC3/E, Fusion
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Port Description |
|
Port Name |
Size |
Type |
Req/Opt |
Function |
|
Data |
decln A |
Input |
Req. |
Input data |
|
Enable |
1 |
Input |
Opt. |
Enable |
|
Eq |
DECODES |
Output |
Req. |
output |
|
A. decln is an integer and log2 (DECODES) = decln d<log2 (DECODES + 1). If decln is equal to 1, then Data is scalar, else Data is a bus. |
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Parameter Description |
|
Parameter |
Value |
Function |
|
DECODES |
2-32 |
Word length of Eq |
|
EN_POLARITY |
0 1 2 |
Enable polarity (active high, active low or not used) |
|
EQ_POLARITY |
0 1 |
Eq polarity (active low or active high) |
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Functional Description A |
|
Data |
Enable |
Eq |
|
X |
0 |
0’s |
|
m |
1 |
dec B (m)==decodes-1 && C dec(m)==decodes-2 && … && dec(m)==0 |
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A. Assume enable is active low and Eq is active high. B. dec(m) defines the decimal value of m C. && indicates bity concatenation |