See the SmartGen Cores Reference Guide for additional information on this core.
Parameterized word length
Optional Carry-out signals
One very fast gate-level
implementation, FC High Speed
and FC Ripple available
Behavioral simulation model in VHDL and Verilog
ACT 2, ACT 3, 3200DX, MX, SX, SX-A, eX, 500K, PA, Axcelerator, ProASIC3/E, Fusion
|
Port Description |
|
Port Name |
Size |
Type |
Req/Opt |
Function |
|
DataA |
WIDTH |
Input |
Req. |
Input Data |
|
Sum |
WIDTH |
Output |
Req. |
Sum |
|
Cout |
1 |
Output |
Opt. |
Carry-out |
|
Parameter Description |
|
Parameter |
Value |
Function |
|
WIDTH |
2-32 2-156 for FC_FDEC and FC_RIPDEC |
Word length of DataA and Sum |
|
CO_POLARITY |
0 1 2 |
Carry-out polarity (active low, active high, and not used) |
|
Implementation Parameters |
|
Parameter |
Value |
Description |
|
LPMTYPE |
LPM_ADD_SUB |
Decrementer category |
|
LPM_HINT |
FDEC FC_FDEC and FC_RIPDEC, Fast Carry Versions |
Very fast carry look ahead |
|
Functional Description |
|
DataA |
DataB |
Sum |
Cout |
|
m |
n |
m - 1 |
(m-1) < 0 |