Parameterized word length and depth
Dual-port RAM architecture
Asynchronous, synchronous-transparent or synchronous-pipelined read
Asynchronous, or synchronous write
Parity check or generate, both even and odd
Supported netlist formats: EDIF, VHDL and Verilog
500K, PA
There is no limitation for depth and width. However, it is your responsibility to insure that the FIFOs used in a design can physically fit on the device chosen for the design.
|
Port Description |
|
Port Name |
Size |
Type |
Req/Opt |
Function |
|
DI<0:8> |
9 |
Input |
Req. |
Input data bits <0:8>; <8> can be used for parity In |
|
LEVEL |
8A |
Input |
Opt. |
Defines level when EQTH and GEQTH should react (hardcoded for static trigger level) |
|
WRB |
1 |
Input |
Req. |
Write pulse (active low) |
|
RDB |
1 |
Input |
Req. |
Read pulse (active low) |
|
WCLK |
1 |
Input |
Req. |
Write Clock (active high) |
|
RCLK |
1 |
Input |
Req. |
Read Clock (active low) |
|
RESET |
1 |
Input |
Req. |
Reset for FIFO pointers (active low) |
|
DO<0:8> |
9 |
Output |
Req. |
Output data bits <0:8>, <8> can be used for parity Out |
|
EMPTY |
1 |
Output |
Req. |
Empty flag |
|
FULL |
1 |
Output |
Req. |
Full flag |
|
EQTH |
1 |
Output |
Req. |
Flag is true when FIFO hold (LEVEL) words |
|
GEQTH |
1 |
Output |
Req. |
Flag is true when FIFO hold (LEVEL) words or more |
|
PI |
WIDTH |
Input |
Opt. |
Input parity bits |
|
PO |
log2 |
Output |
Opt. |
Parity bits |
|
WPE |
1 |
Output |
Opt. |
Write parity error flag (active High), available only for parity checking models |
|
RPE |
1 |
Output |
Opt. |
Read parity error flag (active High); available only for parity checking models |
|
PARODD |
1 |
Input |
Opt. |
Selects Odd parity generation/detect when High; selects Even parity when Low |
A. LEVEL is always eight bits. That means for values of DEPTH greater than 256 not all values will be possible, e.g. for DEPTH =512, LEVEL can have the values 2, 4, … , 512.
This holds true only to dynamically triggered FIFO. For a static trigger, all values of the depth are possible. In the case of dynamic trigger, only values that are divisible by the number of 256X9 FIFO blocks cascaded to achieve the required depth are possible.
In simulation, EQTH/GEQTH reacts to LEVEL * [# of 256x9 modules (rounded up)].
For example, with 1000x32 sync dynamic, level=1, EQTH/GEQTH toggles after 4 reads.
For a 700x32 sync dynamic, level=1, EQTH/GEQTH toggles after 3 reads.
|
Parameter Description |
|
Parameter |
Value |
Function |
|
WIDTH |
width |
Word length of DI and DO |
|
DEPTH |
depth |
Number of RAM words |
|
RDA |
async transparent pipelined |
Read Data Access |
|
WRA |
async sync |
Write Data Access |
|
OPT |
speed area |
Optimization |
|
PARITY |
checkeven checkodd geneven genodd none |
Parity check or parity generation |
|
Implementation Parameters |
|
Parameter |
Value |
Description |
|
LPMTYPE |
LPM_FIFO_DQ |
Generic FIFO category |
|
LPM_HINT |
FIFO_DYN |
FIFO with dynamic trigger level |
|
LPM_HINT |
FIFO_STATIC |
FIFO with static trigger level |
|
Parameter Rules for FIFO with static trigger level |
|
Parameter Rules |
|
LEVEL <= DEPTH |
|
If DEPTH > 256 not all values for LEVEL will be available (automatic value correction). This holds true only to dynamically triggered FIFO. For a static trigger, all values of the depth are possible. In the case of dynamic trigger, only values that are divisible by the number of 256X9 FIFO blocks cascaded to achieve the required depth are possible. For example, for a depth of 512, which uses two 256 blocks in cascade, only multiples of 2 are possible. For depth of 768, which uses three blocks, multiples of 3 are the only values possible for the LEVEL threshold. |
Please refer to the timing waveforms presented in the Flash family datasheets. The datasheets are available on the Actel website at http://www.actel.com.