On-chip RAM
Parameterized word length and depth
FIFO full and empty flags
Statically programmable almost full flag to indicate when the FIFO core reaches a specific level, usually when writing into the FIFO
Statically programmable almostempty flag to indicate when the FIFO core reaches a specific level, usually when reading from the FIFO
Global reset of the FIFO address pointers and flag logic
Dual-port synchronous FIFO
3200DX, MX, SX, SX-A, eX
The SmartGen FIFO cores use the 3200DX and MX 32x8 or 64x4 dual-port RAM cells. Addresses are generated internally using counters and token chains to address the RAM (this is transparent to the user). Dedicated read and write address data paths are used in the FIFO architecture. The read and write operations are totally independent and can be performed simultaneously.
The WIDTH (word length) and DEPTH (number of words) have continuous values but the choice of WIDTH limits the choice of DEPTH and vice versa.
The asynchronous clear signal, Aclr, can be active low or active high (low is the default option and should be used for all synchronous elements in the two supported families). When the asynchronous clear is active, all internal registers used to determine the current FIFO read and write addresses (counters and token chains) are reset to 0'.
The FIFO is now in an empty state; the RAM content is not affected. When power is first applied to the FIFO, the FIFO must be initialized with an asynchronous clear cycle to reset the internal address pointers.
The full flag signal, FF, is optional and is available only for the High-Speed Flag (FFIFO) and the Medium-Speed Flag (MFFIFO) variations. The FF signal is active high only (if selected) and indicates when the FIFO is full. The signal is asserted high on the rising (RISE) or falling (FALL) edge of the clock signal Clock with no delay.
The empty flag signal, EF, is optional and is available only for the High-Speed Flag (FFIFO) and the Medium-Speed Flag (MFFIFO) variations. The EF signal is active low only (if selected) and indicates when the FIFO is empty. The signal is asserted low on the rising (RISE) or falling (FALL) edge of the clock signal Clock with no delay.
The write enable signals, WE and WEF, and read enable signals, RE and REF, are active high requests for writing into and reading out of the FIFO respectively. The WE and RE signals only control the logic associated with the FIFO write and read address pointers. The WEF and REF signals control the logic implementing the different flags. The WE and WEF signals should be logically driven by the same logic outside the FIFO core. The same behavior applies to the RE and REF signals as well. For SX and SX-A there are only the RE and WE ports.
When WE is asserted high and FF is asserted low (not full), the write cycle is initiated and Data are written into the FIFO. When WE is asserted high and FF is asserted high (full), the FIFO behavior is undefined. When RE is asserted high and EF is asserted high (empty), the read cycle is initiated and Q is read from the FIFO. When RE is asserted high and EF is asserted low (empty), the FIFO behavior is undefined. When RE and WE are asserted high at the same time, Data are written into the FIFO and Q is read from the FIFO simultaneously. The read and write operations are fully synchronous with respect to the clock signal Clock.
The FIFO function offers a parameterizable almost-full flag, AFF. The AFF flag is asserted high when the FIFO contains aff_val words or more as defined by the parameter AFF_VAL. Otherwise, AFF is asserted low. The aff_val value is a parameter to the core, and thus logic is built at generation time to realize the almost-full flag function.
The FIFO function offers a parameterizable almost-empty flag, AEF. The AEF flag is asserted low when the FIFO contains aef_val words or less as defined by the parameter AEF_VAL. Otherwise, AEF is asserted high. The aef_val value is a parameter to the core, and thus logic is built at generation time to realize the almost-empty flag function.
|
Port Description |
|
Port Name |
Size |
Type |
Req./Opt. |
Function |
|
Data |
WIDTH |
Input |
Req. |
Input Data |
|
WE |
1 |
Input |
Req. |
Write Enable with the FIFO only (noflag) |
|
RE |
1 |
Input |
Req. |
Read Enable with the FIFO only (no flag) |
|
WEF |
1 |
Input |
Req. |
Write enable associated with the flag logic only (for DX/MX) |
|
REF |
1 |
Input |
Req. |
Read enable associated with the flag logic only (for DX/MX) |
|
Clock |
1 |
Input |
Req. |
Write and read clock |
|
Q |
WIDTH |
Output |
Req. |
Output Data |
|
FF |
1 |
Output |
Req. |
Full Flag |
|
EF |
1 |
Output |
Req. |
Empty Flag |
|
AFF |
1 |
Output |
Optional |
Almost Full Flag |
|
AEF |
1 |
Output |
Optional |
Almost Empty Flag |
|
Parameter Description |
|
Parameter |
Value |
Function |
|
WIDTH |
Width |
Word length of Data and Q |
|
DEPTH |
Depth |
Number of FIFO words |
|
FF_POLOARITY |
1 2 |
FF can be active high or not |
|
EF_POLARITY |
0 2 |
EF can be active low or not used |
|
AFF_VAL |
aff_val (see parameter rules) |
AFF value (not used if aff_val is 0 |
|
AEF_VAL |
aef_val (see parameter rules |
AEF value (not used if aef_val is 0 |
|
CLK_EDGE |
RISE FALL |
Clock can be rising or falling |
|
Implementation Parameters - MX/DX |
|
Parameter |
Value |
Description |
|
LPMTYPE |
LPM_FIFO_DQ |
Generic FIFO category |
|
LPM_HINT |
FFIFO |
High speed FIFO with flags |
|
MFFIFO |
Medium speed FIFO with flags |
|
Implementation Parameters - SX/SX-A |
|
Parameter |
Value |
Description |
|
LPM_HINT |
FFIFOSX |
Synchronous FIFO with no flags |
|
Fan-in Parameters |
|
Parameter |
Value |
Description |
|
RAMFANIN |
AUTO MANUAL |
See Fan-in Control section in online help |
|
Parameter Rules |
|
Parameter Rules |
|
If RCLK_EDGE is NONE (Asynchronous mode), then RE_POLARITY must be 2 (not used) |
Timing waveforms for this core are available in the SmartGen Cores Reference Guide. The reference guide is located in the Designer\doc directory on the hard drive where you installed your Actel Libero IDE or Designer software.