Synchronous/Asynchronous Dual Port RAM for ProASIC and ProASICPLUS

There is no limitation for depth and width. However, it is your responsibility to insure that the RAM’s used in a design can physically fit on the device chosen for the design.

Port Name	Size	Type	Req/Opt?	Function
DI	WIDTH	Input	Req.	Input Data
RADDR	log2 (DEPTH)	Input	Req.	Read Address
WADDR	log2 (DEPTH)	Input	Req.	Write Address
WRB	1	Input	Req.	Write pulse (active low )
DIS	1	Input	Opt.	DMUX select; please refer to the Deep Memories section of the ProASICPLUS RAM/FIFO blocks application note
RDB	1	Input	Req.	Read pulse (active low )
WCLK	1	Input	Req.	Write Clock (active high)
RCLK	1	Input	Req.	Read Clock (active high)
DO	WIDTH	Output	Req.	Output data
DOS	1	Output	Opt.	DMUX select; please refer to the Deep Memories section of the ProASICPLUS RAM/FIFO blocks application note
PI	WIDTH	Input	Opt.	Input parity bits
PO	log2(WIDTH)	Output	Opt.	Parity bits
WPE	1	Output	Opt.	Write parity error flag
RPE	1	Output	Opt.	Read parity error flag

Parameter	Value	Function
WIDTH	Width	Word length of DI and DO
DEPTH	Depth	Number of RAM words
RDA	async transparent pipelined	Read Data Access
WRA	async sync	Write Data Access
OPT	speed area	Optimization
PARITY	checkeven checkodd geneven genodd none	Parity check or parity generation

Timing Waveforms

Please refer to the timing waveforms presented in the Flash family datasheets. The datasheets are available on the Actel website at http://www.actel.com.

Parameter	Value	Description
LPMTYPE	LPM_RAM_DQ	Generic Dual Port RAM category

Synchronous/Asynchronous Dual-Port RAM for ProASIC and ProASICPLUS

Features

Family Support

Description

Timing Waveforms