Please refer to the Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs application note, available on the Actel website (http://www.actel.com), for a complete explanation of the EDAC RAM module.
8-, 16-, 32-bit word width
Background refresh and variable refresh rate
EDAC RAM module supports READ and WRITE clocks from the same clock source OR separate READ and WRITE clocks
EDAC RAM Encoder/Decoder supports correcting one error and detecting two errors, with a coding efficiency of 44-66%
Variable RAM depth support from 256 to 4k words
Axcelerator
The Error Detection and Correction (EDAC) RAM module is designed to provide a transparent RAM interface that supports EDAC. When you use SmartGen to generate an EDAC RAM module, it creates a top level for the EDAC RAM, an Axcelerator RAM block, and the "edaci" module, which handles all the EDAC functionality.