Please refer to the Memory in Flash Devices chapter of the SmartGen Core Reference Guide for more detailed descriptions of Distributed Memories for Flash devices.
Parameterized word length and depth
Asynchronous FIFO
Asynchronous, or synchronous write
Rising-edge triggered or level-sensitive
Supported netlist formats: VHDL and Verilog
500K, PA
Distributed memory can be generated as a two-port asynchronous register file or as an asynchronous FIFO. Distributed memories are made up of the logic tiles of the device. These memory files are netlists consisting of logic tiles and do not use to embedded memory cells.
|
Port Description |
|
Port Name |
Size |
Type |
Req/Opt? |
Function |
|
wData<i> |
1 |
Input |
Req. |
Input (Write) Data (i = 0 .. WIDTH-1) |
|
INIT |
1 |
Input |
Req. |
FIFO initialization |
|
WR |
1 |
Input |
Req. |
Write Clock/Pulse (rising edge triggered or level sensitive) |
|
RD |
1 |
Input |
Req. |
Read Clock/Pulse (rising edge triggered or level sensitive) |
|
rData<i> |
1 |
Output |
Req. |
Output (Read) Data (i = 0 .. WIDTH-1) |
|
full |
1 |
Output |
Req. |
Full Flag |
|
empty |
1 |
Output |
Req. |
Empty Flag |
|
Parameter Description |
|
Parameter |
Value |
Function |
|
WIDTH |
See Parameter Rules |
Word length input/output data |
|
DEPTH |
2..64 |
Number of words |
|
TRIGGER |
edge, level |
Select between rising- edge triggered and level-sensitive write clock |
|
Implementation Parameters |
|
Parameter |
Value |
Description |
|
LPMTYPE |
LPM_DIST_FIFO |
Generic distributed FIFO category |
|
LPM_HINT |
FIFO_DISTH<#> |
Horizontal Orientation |
|
FIFO_DISTV<#> |
Vertical Orientation |
|
Parameter Rules |
|
Device |
Orientation |
Parameter Rules |
|
A500K050 |
Horizontal |
WIDTH = 2..62, DEPTH = 2..36 |
|
Vertical |
WIDTH = 2..94, DEPTH = 2..23 | |
|
A500K130 |
Horizontal |
WIDTH = 2..78, DEPTH = 2..62 |
|
Vertical |
WIDTH = 2..158, DEPTH = 2..29 | |
|
A500K180 |
Horizontal |
WIDTH = 2..94, DEPTH = 2..74 |
|
Vertical |
WIDTH = 2..190, DEPTH = 2..36 | |
|
A500K270 |
Horizontal |
WIDTH = 2..118, DEPTH = 2..80 |
|
Vertical |
WIDTH = 2..222, DEPTH = 2..45 | |
|
APA075 |
Horizontal |
WIDTH = 2..22, DEPTH = 2..64 |
|
Vertical |
WIDTH = 2..62, DEPTH = 2..48 | |
|
APA150 |
Horizontal |
WIDTH = 2..46, DEPTH = 2..49 |
|
Vertical |
WIDTH = 2..126, DEPTH = 2..16 | |
|
APA300 |
Horizontal |
WIDTH = 2..62, DEPTH = 2..49 |
|
Vertical |
WIDTH = 2..126, DEPTH = 2..23 | |
|
APA450 |
Horizontal |
WIDTH = 2..62, DEPTH = 2..74 |
|
Vertical |
WIDTH = 2..190, DEPTH = 2..23 | |
|
APA600 |
Horizontal |
WIDTH = 2..94, DEPTH = 2..80 |
|
Vertical |
WIDTH = 2..222, DEPTH = 2..36 | |
|
APA750 |
Horizontal |
WIDTH = 2..126, DEPTH = 2..80 |
|
Vertical |
WIDTH = 2..254, DEPTH = 2..49 | |
|
APA1000 |
Horizontal |
WIDTH = 2..158, DEPTH = 2..80 |
|
Vertical |
WIDTH = 2..350, DEPTH = 2..62 |
Please refer to the timing waveforms in the Memory for Flash Devices chapter of the SmartGen Cores Reference Guide for more information. The reference guide is available in the Designer\doc directory on the machine where you installed your Actel software.