Variable input data width: 2- to 16-bit input data
Variable output data width: 3- to 64 bit output data
Support for up to 64 taps
Support of symmetric coefficients
Optional I/O insertion
Optional registers for filter in- and output
Verilog RTL model for simulation
VHDL RTL model for synthesis (synthesized filter designs are usually slower, but more compact)
SX, SX-A, 500K, PA, Axcelerator, ProASIC3/E, Fusion
An overview of the design flow required for the FIR filter is shown in the figure below.
Generate the filter coefficients and other implementation parameters using a system level design tool (like Matlab). This information is made available for SmartGen in form of a <design>.gen file.
From that point on, it follows the regular design flow as described in the Actel Quick Start Guide.
The SmartGen FIR-filter core supports symmetric, high-speed, parallel FIR-filters with up to 64 time taps.
Tap Transposed from FIR Filter
The architecture is a variation of the "transposed form" of the FIR filter as shown in the figure above, making use of SmartGen's signed Constant Multiplier. The data is assumed to be signed. Data- and coefficient widths are the same (D_WIDTH).
The FIR filter figure above suggests that coefficients with a value of 0 are desirable for this type of architecture, since they will not generate any multiplication hardware. "Halfband" filters are trying to maximize the number of 0-coefficients and might result in significant area savings over regular filters of the same order.
Port Description |
Port Name |
Size |
Type |
Req/Opt? |
Function |
Data |
D_WIDTH |
input |
Req. |
Input Data |
Clock |
1 |
input |
Req. |
Filter clock |
Aclr |
1 |
input |
Opt. |
Asynchronous Clear |
Qout |
O_WIDTH |
input |
Req. |
Filter output = S ci * di |
Parameter Description |
Parameter |
Value |
Function |
D_WIDTH |
3 .. 16 |
Input Data Width |
O_WIDTH |
3 .. 64 |
Output Data Width |
TAPS |
3 .. 64 |
Number of time taps |
CLK_EDGE |
RISE FALL |
Clock sensitivity |
CLR_POLA |
2 0 1 |
None, active high, active low |
PREC |
|
Internal precision |
INSERT_PAD |
NO YES |
Pad insertion |
INSERT_IOREG |
NO YES |
Register inputs and outputs |
C1 … C32 |
0 .. 2C_WIDTH |
Two's-Complement coefficients (integers) |
The output width O_WIDTH has no impact on the filter size. Internally, SmartGen always uses the maximum precision filter, unless specified otherwise using the internal precision parameter PREC. If you set O_WIDTH to 0, SmartGen usese the maximum output resolution (MAX_RES). For values of O_WIDTH greater than MAX_RES, the result is sign-extended. For values of O_WIDTH smaller than MAX_RES, SmartGen cuts some of the lower bits. An upper estimate for MAX_RES is
MAX_RES ≤ 2 × D_WIDTH + [log2(TAPS)]
For example, a 12-tap filter with 8-bit data and coefficients might yield up to (8 + 8 + 4 ) bits = 20-bit output resolution.
The coefficients C1 to C16 are positive integers, which will be interpreted as Two's-Complement numbers. That means 0 to 2C_WIDTH-1-1 are considered positive, and 2C_WIDTH-1-1 to 2C_WIDTH-1 will be interpreted as negative numbers.
Only unique coefficients need to be specified properly, all other coefficients need to be set to any value, e.g. '0'. An N-tap filter requires (N / 2) + (N % 2) unique coefficients.
Only unique coefficients need to be specified properly, all other coefficients need to be set to any value, e.g. '0'. An N-tap filter requires (N / 2) + (N % 2) unique coefficients.
Parameter Rules |
Family |
Variation |
Parameter Rules |
All |
FIR2 |
PREC >= O_WIDTH |
SX, SX-A |
All |
O_WIDTH <= 32 |
SX, SX-A |
All |
TAPS <= 32 |
Implementation Parameters |
Parameter |
Value |
Description |
LPMTYPE |
LPM_FIR |
FIR-filter category |
LPM_HINT |
FIR1 |
Basic options |
FIR2 |
Advanced options |
Internal Precision (PREC) |
Variation |
Value |
Description |
Basic Options |
97, 0 |
Maximum output resolution, same as O_WIDTH |
Advanced Options |
PREC |
See parameter rules |
Internal Precision (PREC) specifies the minimum number of bits:
• For the time tab registers
• From multiplier outputs kept for further processing
• From adder outputs kept for further processing
Currently, the RTL-model does not reflect the PREC parameter, so there may be differences between the simulated output of the structural netlist and the RTL-model for the low-order bits.
The Integer Values Coefficient File consists of the conversion of the quantized coefficients into regular integers. This file can be directly imported into SmartGen.
Sample Integer Coefficient File |
2048 2037 0 48 2048 1892 0 630 1026 630 0 1892 2048 48 0 2037 2048 |