Parameterized word length
Optional Carry-out signals
One very fast gate-level implementation
Behavioral simulation model in VHDL and Verilog
ACT 2, ACT 3, 3200DX, MX, SX, SX-A, eX, 500K, PA,Axcelerator, ProASIC3/E, Fusion
|
Port Description |
|
Port Name |
Size |
Type |
Req/Opt |
Function |
|
DataA |
WIDTH |
Input |
Req. |
Input Data |
|
Sum |
WIDTH |
Output |
Req. |
Sum |
|
Cout |
1 |
Output |
Opt. |
Carry-out |
|
Incdec |
1 |
Input |
Req. |
Increment (Incdec = 1) or decrement (Incdec = 0) |
|
Parameter Description |
|
Parameter |
Value |
Function |
|
WIDTH |
2-32 2-156 for FC_FINCDEC and FC_RIPINCDEC |
Word length of DataA and Sum |
|
CO_POLARITY |
0 1 2 |
Carry-out polarity (active low, active high, and not used) |
|
Implementation Parameters |
|
Parameter |
Value |
Description |
|
LPMTYPE |
LPM_ADD_SUB |
Incrementer/Decrementer category |
|
LPM_HINT |
FINCDEC FC_FINCDEC FC_RIPINCDEC |
Very fast carry look ahead |
|
Functional Description |
|
DataA |
Incdec |
Sum |
Cout |
|
m |
1 |
m + 1 |
(m + 1) less than or equal to 2width |
|
m |
0 |
m - 1 |
(m - 1) < 0 |