Logic (AND)Logic (AND)Parameterized AND size
Behavioral simulation model in VHDL and Verilog
ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, eX, 500K, PA,Axcelerator, ProASIC3/E, Fusion
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Port Description |
|
Port Name |
Size |
Type |
Req/Opt |
Function |
|
Data |
SIZE |
input |
Req. |
Input data |
|
Result |
1 |
Output |
Req. |
Output |
|
Parameter Description |
|
Parameter |
Value |
Function |
|
SIZE |
2-64 |
Word length of data |
|
RESULT_POLARITY |
0 1 |
Output polarity (active low or active high) |
|
Functional Description A |
|
Data |
Result |
|
m |
m[0] and m[1] and … and m[SIZE-1] |
|
A. Result is active; highresult is active high. |