Multiplier

Features

• Parameterized word lengths and constant values

• Unsigned and signed (Two’s-Complement) data representation

• Booth or array implementation

• Optional pipelining

• Behavioral simulation model in VHDL and Verilog

Family Support

ACT 2, ACT 3, 3200DX, MX, SX, SX-A, eX, 500K, PA, Axcelerator, ProASIC3/E, Fusion

For information on the Fast Carry Chain associated with the Axcelerator device, click here.

Description

A. For some of the multiplier variations there are small deviations from the limits mentioned to ensure that the multiplier fits in the largest device of the selected family.

B. TMR: Triple Module Redundancy. Choosing this option makes SmartGen use TMR Flip-Flops which are used to avoid Single Event Upsets (SEUs) for Rad-hard Designs. Choosing this option causes the Sequential resource usage to be tripled in families where no TMR is implemented in silicon.
CC: When combinatorial option is chosen for the Sequential Type, the FF is implemented using two Combinatorial Cells instead of one Sequential Cell. This is useful when no Sequential resources are available in the designs.

This option is applicable only to the pipelined multipliers.

In the Architecture Comparison tables below, WIDTHA = WIDTHB.

Advanced Options

Click the Advanced button (available for PA, 500K, and Axcelerator devices) to specify pipeline stages. If you are using a PA or 500K device, you can insert (default setting) or omit the final Adder stage.

Omitting the Final Adder

You can choose not to instantiate the final adder in the multiplier and add up the two buses Mult0 and Mult1  to the final result later in the design flow. This is often the most efficient implementation when a lot of partial results get summed up in a large summation network. The figure below shows an example for Y = (A x B) + C + D using the multiplier with two outputs in combination with the Array-Adder.

Efficient implementation using the two-output multiplier in combination with the Array-Adder

Multiplier Pipelining

For ProASIC, ProASICPLUS, and Axcelerator devices you can specify the number of pipeline stages (1, 2, or 3). However, three pipeline stages increases performance only for high bitwidth. Click the Advanced button in the GUI to access pipelining.

For ACT 2, ACT 3, 3200DX, MX, SX, SX-A, and eX  the multiplier architecture does not allow you to select the latency of the pipelined multiplier or the number of logic levels between the pipeline stages. Registers are automatically inserted between the major components of the architecture, primarily the multiplexor and adder cores, as shown in the figure below.

Booth Multiplier Architecture (Pipeline)

The number of pipeline stages is a function of the width of the DataB input. The number of logic levels per pipeline stage is a function of the width of the DataA input. Therefore, the number of logic levels per pipeline stage is equal to the number of logic levels of the first adder (WIDTHA + 1) plus 1 for the 4 to 1 multiplexor, as shown in the figure above.

For more information on the Fast Carry-Chain cores available with the Axcelerator family, please refer to Fast Carry Chains (Axcelerator only).