See the SmartGen Cores Reference Guide for additional information on this core.
Parameterized word length
Optional carry-in and carry-out signals
Multiple gate-level implementations (speed/area tradeoffs)
Behavioral simulation model in VHDL and Verilog
ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, eX, 500K, PA, Axcelerator, ProASIC3/E, Fusion
|
Port Description |
|
Port Name |
Size |
Type |
Req/Opt |
Function |
|
DataA |
WIDTH |
Input |
Req. |
Input Data |
|
DataB |
WIDTH |
Input |
Req. |
Input Data |
|
Cin |
1 |
Input |
Opt. |
Carry-in |
|
Sum |
WIDTH |
Output |
Req. |
Sum |
|
Cout |
1 |
Output |
Opt. |
Carry-out |
|
Parameter Description |
|
Parameter |
Family |
Value |
Function |
|
WIDTH A |
500K, PA |
2-128 |
Word length of DataA, DataB and Sum |
|
Axcelerator |
2-156 |
||
|
All others |
2-32 |
||
|
MAXFANOUT |
500K, PA |
0 |
Automatic choice |
|
2-16 |
Manual setting of Max. Fanout | ||
|
CI_POLARITY |
ALL |
0 1 2 |
Carry-in polarity (active low, active high, and not used) |
|
CO_POLARITY |
ALL |
0 1 2 |
Carry-out polarity (active low, active high,and not used) |
A. The Brent-Kung Subtractor extends the ranges from 32 to 128 bit for SX, SX-A and from 20 to 128 bit for 500K.
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Implementation Parameters |
|
Parameter |
Family |
ValueJK |
Description |
|
LPMTYPE |
All |
LPM_ADD_SUB |
Adder category |
|
LPM_HINT |
500K, PA |
SKSUB |
Sklansky model |
|
FBKSUB |
Fast Brent-Kung model | ||
|
BKSUB |
Compact Brent-Kung model | ||
|
ALL |
FSUB A |
Very fast carry select model | |
|
MFSUBA |
Fast carry select model | ||
|
RIPSUB |
Ripple carry model | ||
|
LPMTYPE |
Axcelerator |
LPM_FC_ADD_SUB |
Fast carry chain Adder category |
|
LPM_HINT |
FC_FSUB |
Fast carry chain carry select model | |
|
FC_RIPSUB |
Fast carry chain ripple carry model |
A. FSUB and MFSUB are not recommended for Flash devices.
|
Functional Description |
|
DataA |
DataB |
Sum |
Cout A |
|
m[width-1 : 0] |
n[width-1 : 0] |
(m - n - Cin) [width-1 : 0] |
(m - n - Cin)[width] |
|
A. Cin and Cout are assumed to be active high. |