SmartGen PLL signal descriptions

Name

Size

Type

Required/ Optional

Function

GLA  

1

Output

Req

Primary clock output

CLKA

1

Input

Req

Reference clock

POWERDOWN

1

Input

Req

Power Down Signal. A low on this signal turns off the PLL

LOCK

1

Output

Req

PLL lock

EXTFB

1

Input

Opt

External feedback

GLB

1

Output

Opt

Global Output for Secondary1 Clock

YB

1

Output

Opt

Core Output for Secondary1 Clock

GLC

1

Output

Opt

Global Output for Secondary2 Clock

YC

1

Output

Opt

Core Output for Secondary2 Clock