The RAM Content Manager enables you to specify the contents of your memory so that you can avoid the simulation cycles required for initializing the memory, which improves (reduces) simulation runtime.
The SmartGen RAM core generator takes away much of the complexity required in the generation of large RAMs that utilize 1 or more of the RAM blocks on the device. SmartGen generates a RAM to match your configuration by the total number of memory blocks required and creating the required surrounding logic to cascade them.
SmartGen cascades RAM blocks in 3 different ways.
Cascaded deep (e.g. 2 blocks of 4096x1 to create a 8192x1)
Cascaded wide (e.g. 2 blocks of 4096x1 to create a 4096x2)
Cascaded wide and deep (e.g. 4 blocks of 4096x1 to create a 8192x2, in a 2 blocks width-wise by 2 blocks depth-wise configuration)
You specify memory content in terms of your memory size. SmartGen must partition your memory file appropriately such that the right content goes to the right block RAM when multiple blocks are cascaded.
A standard format created by Intel. Memory contents are stored in ASCII files using hexadecimal characters. Each file is made of a series of records (lines of text) delimited by new line, ‘\n’, characters and each record starts with a ‘:’ character. For more information regarding this format, refer to the Intel-Hex Record Format Specification document available on the web (search Intel Hexadecimal Object File for several examples).
This format uses ASCII files, hex characters, and records to specify memory content in much the same way that Intel-Hex does. Refer to the Motorola S-record description document for more information on this format (search Motorola S-record description for several examples). The RAM Content Manager uses only the S1 through S3 record types; the others are ignored.
The major difference between Intel-Hex and Motorola S is the record formats, and some extra error checking features that are incorporated into Motorola S.
In both formats, memory content is specified by providing a starting address and a data set. The upper bits of the data set are loaded into the starting address and leftovers overflow into the adjacent addresses until the entire data set has been used.
The Actel implementation of these formats interprets data sets in bytes. This means that if the memory width is 7 bits, every 8th bit in the data set is ignored. Or, if the data width is 9, two bytes are assigned to each memory address and the upper 7 bits of each 2-byte pair are ignored.