Various devices in the family have RAM Blocks ranging from 32 to 256 in number, resulting in a total on-chip memory of 144K – 1152K. Each memory block has a total of 4608 bits of memory. Each RAM block has a dedicated FIFO Counter and FIFO Logic attached to it.
Variable aspect ratios of 4096x1, 2048x2, 1024x4, 512x9 and 256X18
Four FIFO flags: empty, full, almost-empty, almost-full
FIFO empty/ full flags synchronized to read clock and write clock, respectively
Programmable threshold values of almost flags
Different read and write aspect ratios
Active Low Asynchronous Reset
Active Low Block Enable
Active Low Write Enable and Active High Read Enable
FSTOP and ESTOP that allow the counters in the FIFO to count after FIFO is full or empty
WW and RW
These signals enable the FIFO to be configured into one of the four allowable aspect ratios.
|
WW2, WW1, WW0 |
RW2, RW1, RW0 |
W x D |
|
000 |
000 |
1 x 4K |
|
001 |
001 |
2 x 2K |
|
010 |
010 |
4 x 1K |
|
011 |
011 |
9 x 512 |
|
100 |
100 |
18 x 256 |
|
101, 110, 111 |
101, 110,111 |
ILLEGAL |
WBLKB and RBLKB
These signals are active low and will enable the respective ports when low. When BLK signals are high the output holds the previous value.
WEN and REN
Read and Write Enables. WEN is Active Low and REN is Active High.
WCLK and RCLK
These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver.
PIPE
This signal is used to specify pipelined read on the output. A Low on the PIPE indicates a non-pipelined read and the data appears on the output in the same clock cycle. A High indicates a pipelined read and data appears on the output in the next clock cycle.
RESET
This Active Low signal resets the output to zero when asserted. It resets the FIFO counters. It also sets all the RD pins low, the FULL and AFULL pins low, and the EMPTY and AEMPTY pins high.
WD
This is the input data signals and is 18 bits wide. But not all 18 bits are valid in all configurations. When a data width less than 18 is specified unused higher order signals must be grounded
|
W x D |
WD UNUSED |
|
1 x 4K |
WD[17:1] |
|
2 x 2K |
WD[17:2] |
|
4 x 1K |
WD[17:4] |
|
9 x 512 |
WD[17:9] |
|
18 x 256 |
N/A |
RD
This is the output data signals and is 18 bits wide. But not all 18 bits are valid in all configurations. Similar to the WD higher order bits become unusable. The output data on unused pins is undefined.
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e. the EMPTY flag goes high). A high on this signal prevents the counting.
FSTOP is used to stop the FIFO write counter from further counting once the FIFO is full (i.e. the FULL flag goes high). A high on this signal prevents the counting.
For more information on these signals refer to the ESTOP, FSTOP Usage section.
FULL, EMPTY
When the FIFO is full and no more data can be written the FULL flag asserts high. It de-asserts after one read operation, when the FIFO is no longer full.
When the FIFO is empty and no more data can be read the EMPTY flag asserts high. It de-asserts after one write operation, when the FIFO is no longer empty.
For more information on these signals please refer to the FIFO Flags Usage section.
AFULL, AEMPTY
These are programmable flags and will assert on the threshold specified by AFVAL and AEVAL respectively.
When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output will go high. Likewise when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go high.
AFVAL, AEVAL
The AEVAL and AFVAL pins are used to specify the almost empty and almost full threshold values, respectively. They are 12 bit signals. For more information on these signals please refer to the FIFO Flags Usage section.
|
Operation |
Address |
RCLK |
WCLK |
RBLK_B |
WBLK_B |
WMODE |
WEN_B |
FIFO |
RESET_B |
EF |
FF |
EF_STOP |
FF_STOP |
DI |
DO |
|
FIFO Reset |
X |
X |
X |
X |
X |
X |
X |
H |
L |
H |
L |
X |
X |
X |
L |
|
Operation |
Address |
RCLK |
RBLK_B |
REN |
FIFO |
RESET_B |
EF |
FF |
EF_STOP |
DI |
DO |
|
FIFO Read |
RA-Current |
Rising Edge |
L |
H |
H |
H |
L |
Z |
Z |
Z |
Data |
|
FIFO Empty (*1) |
RA-Last |
Rising Edge |
L |
H |
H |
H |
H |
L |
H |
X |
Data - Last |
|
FIFO Empty (*2) |
RA - Current |
Rising Edge |
L |
H |
H |
H |
H |
L |
L |
X |
Data |
|
Operation |
Address |
WCLK |
WBLK_B |
WMODE |
WENB |
FIFO |
RESET_B |
EF |
FF |
FF_STOP |
DI |
DO |
|
FIFO Write |
WA-Current |
Rising Edge |
L |
L |
L |
H |
H |
X |
L |
X |
Data |
Data - Last |
|
FIFO Full (*3) |
WA-Last |
Rising Edge |
L |
L |
L |
H |
H |
L |
H |
H |
X |
Data - Last |
|
FIFO Full (*4) |
WA - Current |
Rising Edge |
L |
L |
L |
H |
H |
L |
H |
L |
Data |
Data - Last |
(*1) Empty flag high inhibits read counter forward counting. Data bus holds the last read out data.
(*2) Empty flag high does not stop read counter. Old data is read out again.
(*3) Full flag high stops write counter for further count. No more write until full flag goes low.
(*4) Full flag high does not stop write counter. Unread data was overwritten by data