ProASIC3E RAM4K9

Features

RAM4K9 is a true dual port RAM and it supports the following features.

• Variable aspect ratios of 4096x1, 2048x2, 1024x4 and 512x9

• Two Independent ports capable of being used for Read or Write

• Allowable Dual Port Usage: Both Read, Both Write, One Read & One Write; Same Clock Frequency or Different Clock Frequencies

• Synchronous Write and Pipelined or Non-Pipelined Synchronous Read

• Active Low Asynchronous Output Reset

• Active Low Block Enable for both ports

• Capability of choosing pass-through of Write Data or hold old Data on Output

Description

The following signals are used to configure the RAM4Kx9 memory element.

WIDTHA and WIDTHB

These signals enable the RAM to be configured into one of the four allowable aspect ratios.

BLKA and BLKB

These signals are active low and will enable the respective ports when asserted. When BLK signals are de-asserted the output holds the previous value.

WENA and WENB

These signals switch the RAM between Read and Write modes for the respective ports. A Low on these signals indicates Write operation and a High indicates a Read.

CLKA and CLKB

These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver.

PIPEA and PIPEB

These signals are used to specify pipelined read on the output. A Low on the PIPEA or PIPEB indicates a non-pipelined read and the data appears on the output in the same clock cycle. A High indicates a pipelined read and data appears on the output in the next clock cycle.

WMODEA and WMODEB

These signals are used to configure the behavior of the output when RAM is in the write mode. A Low on this signal makes the output retain data from the previous read. A High indicates a pass-through behavior where the data being written will appear on the output immediately. This signal gets overridden when RAM is being read.

RESET

This Active Low signal resets the output to zero when asserted. It does not reset the content of the memory.

ADDRA and ADDRB

These are used as read or write addresses and are 12 bits wide. When a depth of less than 4K is specified, the unused higher order bits must be grounded.

DINA and DINB

These are the input data signals and are 9 bits wide. But not all 9 bits are valid in all configurations. When a data width less than 9 is specified unused higher order signals must be grounded

DOUTA and DOUTB

These are the output data signals and are 9 bits wide. But not all 9 bits are valid in all configurations. Similar to the DINA and DINB higher order bits become unusable. The output data on unused pins is undefined.

RAM4K9 Truth Table