FlashROM uses the MEM file for simulation.
The MEM file has 128 rows of eight bits, representing the contents of the FlashROM. SmartGen defaults to 0s for any unspecified locations of the FlashROM memory.
During simulation, employ the MEM file, which contains the memory content, along with the design netlist and testbench. The VITAL and Verilog simulation models accept the generics passed by the netlist, read the MEM file, and perform simulation with the data in the file.
In addition to using the MEM file from SmartGen, you may create a binary file with 128 rows of eight bits and save the file as a MEM file. Actel recommends using different names if you plan to generate multiple MEM files. During place-and-route in Designer, the software recognizes the generic property in the netlist and pass the MEM file links through to the output netlist.
If you are using Libero, you can use the synthesis tools to synthesize your design. Libero generates post-synthesis files to use for simulation; use your synthesis tool to generate your EDIF netlist.