The Compile Report appears in the Designer Log window after compile is complete. It is divided into the following sections:
All the information about the design, including the device selection and compile options used to run compile. Some options are not shown if you did not select them; for example, if the option demote_globals is OFF than the option demote_globals_max_fanout does not appear in the report.
Lists any warnings or errors encountered during compile. Also contains the Netlist Optimization report that lists out the optimized macros (deleted blocks) in your design.
Lists out any PDC related errors and warnings encountered during compile.
The Device Utilization Report includes the following:
Complete device utilization: Summary for all the resources used in the final optimized netlist.
Global Information: Describes the number of chip and quadrant clocks in the design and the device.
Core Information: Describes the total number of macros in the netlist and how many tiles they are using.
I/O function: Detailed information about I/O's, such as how many Diff I/Os exist in the netlist, etc.
I/O Technology: Summary of I/O technology used in the netlist.
I/O Bank Resource Usage: Summarizes each I/O bank, including details on voltages, I/O pairs, Vref I/Os, Vref Pins, etc.
I/O Voltage Usage: Lists I/Os by voltage used in the netlist and device resources available for each voltage (using the iobank and placement information).
The section may not appear if there is no net to report. The Net Information Report includes the following sections:
List of nets that drive enable flip-flops that have been remapped to a 2-tile implementation
List of nets that have been assigned to a chip global resource
List of nets that have been assigned to a quadrant global resource
List of nets that nets have been assigned to a LocalClock resource using PDC constraints
High fanout nets in the post-compile netlist
Nets that are candidates for clock assignment and the resulting fanout
Note: If the driver macro of a clock net is fixed in a quadrant clock location then this net will show in the quadrant clock net report.
The number of clock nets (chip+quadrant) can be less than the number reported in the device utilization (such as in the case of PLL using a YB and not the GLB).
Net Information Report Types
INT_NET - Internal nets
CLK_NET - More than 75% of pins driven by this net are clock pins
SET/RESET_NET - More than 75% of pins driven by this net are set or reset pins
Net Information Source Types:
NETLIST - Clock from the netlist
PDC PROMOTED - Promoted because of a PDC constraint
AUTO PROMOTED - Promoted automatically by compile; change the compile options if you do not want to promote this net.
ESSENTIAL - Global clock from the netlist that cannot be demoted (such as the PLL or CLKBIBUF).
Net Information Report Region (Definition)
The region is the clock region for the local and quadrant
clocks. For example,
Local clock regions chip_T1, chip_T2:B5, quandrant_T1
The quadrant clock regions list is as follows: quadrant_UL, quadrant_UR, quadrant_LL, quadrant_LR