max_delays/min_delays

SECTION MAX_DELAYS/MIN_DELAYS

Use the MAX_DELAYS and MIN_DELAYS section to specify the maximum and minimum delays.

DELAY value timeunit; SOURCE {source_name_list}; SINK {sink_name_list}; [STOP {stop_name_list}]; [PASS {bypass_name_list}].

Arguments

DELAY value

Specifies an integer.

timeunit

Allows {PS, NS, US}.

source_name_list

A list of signal sources. It can be one of the following: a macro output pin, macro name, or primary input.

sink_name_list

A list of signal destinations. It can be a name of a macro or a primary output.

stop_name_list

The list of pin names through which further propagation of signals will not be considered. This allows you to eliminate certain paths from consideration.

bypass_name_list

The list of latches which are allowed to be intermediate path points. By default, latches are considered to be sinks or path terminals.

INPAD/OUTPAD/GATED

Valid values for any of the lists, such as source_name_list or stop_name_list.

Normally there is no need to specify any timing requirements from any source to any sink clocked by an external global clock. This timing requirement can be generated automatically from the GLOBAL_CLOCK specifications and the sequential elements setup and hold times. For example, the timing constraint from a primary input to a sequential element can be derived from the sequential elements clocking waveform and the signal arrival time of the primary input.

A problem exists when two different internally-generated clock signals interact. This is due to the unpredictable and unknown skew between the two clock networks because of the routing delays from:

PAD >> internalMacro >> CLKINT

where CLKINT is the input pin of the global clock distribution network. The automatically generated path constraints will not incorporate the skew between the two clocks. In such cases, the path constraints should be expressed explicitly using the MAX/MIN_DELAYS section.

NOTE: The most stringent timing constraint dominates. Hence, all general constraints should be looser than the specific constraints. For example, in the following example, the 26.0ns constraint dominates the 42.0ns constraint:

DELAY 42.0 ns SOURCE INPAD SINK OUTPAD.

DELAY 26.0 ns SOURCE {$1I23:Q $1I24:Q} SINK {ack_0}.

If the general constraint is tighter than the specific constraint, the specific constraint will effectively become a no-operation. In the following example, the looser constraint of 42.0ns has no effect since the general constraint of 26.0ns dominates.

DELAY 26.0 ns SOURCE INPAD SINK OUTPAD.

DELAY 42.0 ns SOURCE {$1I23:Q $1I24:Q} SINK {ack_0}.

The section MAX_DELAYS can be empty if there are no purely combinatorial paths from external sources to external sinks, and if every sequential element in the design is clocked by an external global clock. In this case, the timing constraints are generated automatically using the information in the GLOBAL_CLOCK section. Likewise, the MIN_DELAYS section can be empty.

One final word about external/internal sinks and sources with regard to the flip-flops and/or latches in the IOs: these flip-flops act as internal, not external, sources/sinks.