The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:
|
Families |
PDC |
GCF |
|
Fusion |
X |
|
|
ProASIC3E |
X |
|
|
ProASIC3 |
X |
|
|
ProASIC PLUS |
|
X |
|
Axcelerator |
|
|
|
ProASIC |
|
X |
|
eX |
|
|
|
SX-A |
|
|
|
SX |
|
|
|
MX |
|
|
|
3200DX |
|
|
|
ACT3 |
|
|
|
ACT2/1200XL |
|
|
|
ACT1 |
|
|
Use this constraint to assign high fan-out nets to global clock networks by promoting the net using an internal global macro.
If there are enough global clock routing resources available in a device, you can promote regular nets that have high fan-out to the dedicated fast global clock routing resources which can lead to better performance for your design. This is achieved by automatically inserting an internal global macro on a net which guides the place-and-route tool to promote that particular net to a global clock resource. This internal global macro is CLKINT for ProASIC3/E devices, GLINT for ProASIC PLUS and ProASIC devices, and either HCLKINT or CLKINT for Axcelerator devices.
You can use one or more of the following commands or GUI tools to assign a net to a global clock:
PDC - assign_global_clock
GCF - set_global