Assign net to quadrant clock

Families Supported

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

Families

PDC

ChipPlanner

Fusion

X

X

ProASIC3E

X

X

ProASIC3

X

X

ProASIC PLUS

 

 

Axcelerator

 

 

ProASIC

 

 

eX

 

 

SX-A

 

 

SX

 

 

MX

 

 

3200DX

 

 

ACT3

 

 

ACT2/1200XL

 

 

ACT1

 

 

Purpose

Use this constraint to assign regular nets to quadrant clock routing. This results in the creation of a QuadrantClock region that spans the area of the quadrant clock net.

If there are enough quadrant clock resources but not enough global clock routing resources available in a device, you can promote regular nets that have high fan-out to the dedicated quadrant clock routing resources which can lead to better performance for your design.

Tools /How to Enter

You can use one or more of the following commands or GUI tools to assign a net to a local clock:

See Also

Constraint entry

assign_quadrant_clock (PDC)

Creating QuadrantClock regions