The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:
Families |
PDC |
GCF |
ChipPlanner |
Fusion |
X |
|
X |
ProASIC3E |
X |
|
X |
ProASIC3 |
X |
|
X |
ProASIC PLUS |
|
X |
X |
Axcelerator |
X |
|
X |
ProASIC |
|
X |
X |
eX |
|
|
|
SX-A |
|
|
|
SX |
|
|
|
MX |
|
|
|
3200DX |
|
|
|
ACT3 |
|
|
|
ACT2/1200XL |
|
|
|
ACT1 |
|
|
|
Use this constraint to place all the loads of a net into a given region. This constraint is useful for high fan-out or critical path nets or bus control logic.
Constraining nets to a region helps to control the connection delays from the net's driver to the logic instances it fans out to. You can adjust the size of the region to pack logic more closely together, hence, improving its net delays.
Suppose you have a global net with loads that span across the whole chip. When you constrain this net to a specific region, you force the loads of this global net into the given region. Forcing loads into a region frees up some areas that were previously used. You can then use these free areas for high-speed local clocks/spines.
Macros connected to a specific net can be assigned to a region in the device. The region can be defined using the define_region PDC command. With the set_net_region GCF command, you can use array coordinates to define the region into which you want to place all the connected instances, driver, and all the driven instances for the net(s).
When assigning a net to a region, all of the logic driven by that net will be assigned to that region.
Using Regions for Critical Path and High Fan-out Nets
You should assign high fan-out or critical path nets to a region only after you have used up your global routing and clock spine networks. If you have determined, through timing analysis, that certain long delay nets are creating timing violations, assign them to regions to reduce their delays.
Before creating your region, determine if any logic connected to instances spanned by these nets have any timing requirements. Your region could alter the placement of all logic assigned to it. This may have an undesired side effect of altering the timing delays of some logic paths that cross through the region but are not assigned to it. These paths could fail your timing constraints depending on which net delays have been altered.
You can use one or more of the following commands or GUI tools to assign a net to a region:
PDC - assign_net_macros
GCF - set_net_region
ChipPlanner - Assigning a net to a region