The following table shows which families support this constraint and which tools you can use to enter or modify it:
|
Families |
PDC |
GCF |
Compile Options |
|
Fusion |
X |
|
X |
|
ProASIC3E |
X |
|
X |
|
ProASIC3 |
X |
|
X |
|
ProASIC PLUS |
|
X |
|
|
Axcelerator |
|
|
|
|
ProASIC |
|
X |
|
|
eX |
|
|
|
|
SX-A |
|
|
|
|
SX |
|
|
|
|
MX |
|
|
|
|
3200DX |
|
|
|
|
ACT3 |
|
|
|
|
ACT2/1200XL |
|
|
|
|
ACT1 |
|
|
|
Use this constraint to increase the performance of your design.
If there are enough clock routing resources available in a device, you can promote regular nets that have high fan-out to the dedicated fast clock routing resources which can lead to better performance for your design.
You can use one or more of the following commands or GUI tools to promote a regular net to a global clock net:
PDC - assign_global_clock
GCF file - set_global (backwards compatible for ProASIC families only)
Compile Options - -promote_globals <value>