Error: CMP402: The reference clock pin of PLL <pin_name>, when driven by an I/O cell, must have a fanout of 1.

If the reference clock (CLKA) of a PLL is driven by a regular I/O in the design, then the reference clock is hardwired to an external PAD. Therefore, the net connecting the regular I/O macro and the PLL reference clock must have a fanout equal to 1.  

Action

1. If the reference clock of the PLL must be hardwired to an external PAD, make sure that the regular I/O only drives this reference clock of the PLL macro.

2. If the reference clock of the PLL can be routed to an external PAD, make sure to:

• If you are using SmartGen (recommended flow), chose the “External I/O driven” option to generate the PLL core used in the design.

• If you are not using SmartGen, insert a PLLINT macro before the PLL reference clock to indicate that the regular I/O driving the PLL reference clock should be routed. In this case, the regular I/O output net may have a fanout greater than 1.