Depending on the width x depth configuration chosen for a RAM core, the address space or the data space is not fully used. However, the actual library macro has enough address and data ports to cover the full width x depth spectrum available in the architecture for a RAM block. The unusable input address or data pins must be driven by either GND or VCC. The actual value does not matter since the signal is irrelevant for that macro configuration.
Action
Consider using SmartGen to generate a legal pre-configured RAM or FIFO macro, or,
Make sure to connect all RAM unusable pins to GND or VCC in your design.