Warning: CMP503: Remapped <enable_flip_flop_value> enable flip-flop(s) to a 2-tile implementation because the CLR/PRE pin on the enable flip-flop is not being driven by a global net.

Enable flip-flops with a clear or a preset function have a routing constraint for the ProASIC3/E architecture. The clear or preset pin must be driven by a global network. This global network may be a chip-wide, a quadrant, or a local clock. All enable flip-flops that do not satisfy this constraint are automatically remapped to a 2-tile implementation.

Action

Consider driving the clear or preset pin of enable flip-flops with a global network whenever possible. It is preferable to do so if the fanout of the preset or clear net is relatively high. To do so:

• Instantiate a clock I/O macro in the design if the clear or preset net is driven from a PAD.

• Instantiate an internal clock macro (CLKINT) in the design on the clear or preset net if the net is driven by a core macro.

• Promote a regular clear or preset net in the design by using of the following PDC commands:

a. assign_local_clock

b. assign_global_clock