Info: While analyzing gated clock networks, ambiguities have been found on gates <X, Y, Z>. The timing models of these gates have been simplified for Static Timing Analysis.

Where <x, y, z> are the instance names of the gates.

An input pin on the above gates can propagate both rising and falling events. For a more realistic static timing analysis, SmartTime has chosen the non-inverting event to continue the propagation.