The following is a summary of the GCF to SDC timing constraint conversion output file. The file is generated at the end of the translation inside the design directory.
The top section describes the constraints converted from GCF in addition to any constraints previously in the system (like previous imported SDC or constraints entered in the GUI ).
The GCF to SDC conversion details section describes how each constraint has been translated, and the corresponding status. There are four possible states:
successful: No conflict or ambiguity. The translator stores the valid constraint in the constraints database.
conflict: There is conflict with existing constraints in the constraint database; it is still stored in the constraints database.
ambiguity: The constraint is ambiguous. Some constraints are not stored.
failed: The pin is not a valid clock pin (according to the Timer). The constraint is not stored.
The conflict occurred when processing your current GCF constraint. The translator found that there are constraints already stored in the constraints database that have the same pins and constraint type but different period/delay/cycle values. The translator resolves conflicts according to the following rules:
If a GCF constraint conflicts with existing constraints in the constraints database, the GCF constraint takes precedence (or "wins").
If more than one GCF constraint is set for the same pins and same constraint type, the last constraint listed in the GCF file wins (takes precedence).
The translator processes the GCF timing constraints one by one based on the order they appear in GCF file. The translator checks with the constraints database to discover conflicts with existing constraints. If there is a conflict, the delay/period/cycle in the GCF constraint overrides the data stored in the database.
This rule applied to all timing constraints.
There are ambiguity issues only in the create_clock constraint. When dealing with a create_clock that sets a net, the translator provides a list of potential clock pins from that net. The rules the translator uses to determine which pin to choose are as follows:
Choose the first pin in the potential clock pin list that had been constrained as a clock in the constraints database.
If none of pins had been constrained as a clock in the constraints database, choose a PLL output pin if there is one.
If none of pins had been constrained as clock in the constraints database and there are no PLL output pins, choose the first pin in the list. All other pins are ambiguous and tagged as “AMBIGUITY”.
To apply these rules for create_clock constraints on a net, the translator gets the potential clock pin list for the net from Timer. It then checks with the constraints database to determine the clock to set.
For create_clock constraints on ports (and other elements), the translator only applies the conflict rules to solve merging problems.
##############################
# SDC WRITER VERSION "1.0";
# DESIGN "mydesign";
# DATE "Wed Oct 01 15:57:52 2003";
# VENDOR "Actel";
# PROGRAM "Actel Designer Software Release Designer v5.2 Copyright (C) 1989 2003 Actel Corp. ";
# VERSION "5.2.0.0";
##############################
######## Clock Constraints ########
create_clock -period 48.0000 [get_ports {sport_tsclk_I}]
create_clock -period 24.0000 [get_ports {adsp_ams0_n_I}]
create_clock -period 4.0000 [get_pins {f12:Q}]
create_clock -period 76.0000 [get_ports {up_wr_n_I}]
create_clock -period 2.0000 [get_pins {U2/Core:GLA}]
######## Delay Constraints ########
set_max_delay 3.00 -from [get_ports {dat* }] -to [get_clocks {*}]
set_max_delay 2.00 -from [get_clocks {*}] -to {out}
set_max_delay 4.00 -from [get_pins {s_reg_5:CLK }] -to [get_pins {U15:PAD }]
######## False Path Constraints ########
set_false_path -through [get_pins {invIn:Y }]
set_false_path -from {U_ChipMACa/U_MAC/U_DMA/datareq:CLK \
U_ChipMACa/U_MAC/U_DMA/datareq_1_0:CLK \
U_ChipMACa/U_MAC/U_DMA/datareq_0_0:CLK } -through \
{U_SHRAM*/U_ShRAM*}
######## OutPut load Constraints ########
######## Multicycle Constraints ########
set_multicycle_path 3 -from {ff1:CLK } -through {invIn:A } -to {ff2:D }
set_multicycle_path 2 -from {i2s0/i2sRegs0/i2sConfig[4] }
### GCF to SDC conversion details
# GCF Constraint: create_clock -period 48.000000 sport_tsclk_i
# Status: successful
# SDC: create_clock -period 48.000000 [get_ports {sport_tsclk_I}]
# GCF Constraint: create_clock -period 24.000000 adsp_ams0_n_I
# Status: conflict
# SDC: create_clock -period 24.000000 [get_ports {adsp_ams0_n_I}]
# alt: create_clock -period 76.000000 [get_ports {adsp_ams0_n_I}]
# GCF Constraint: create_clock -period 4.000000 andout
# Status: ambiguity
# Translated from net to potential clock f12:Q
# SDC: create_clock -period 4.000000 [get_pins {f12:Q}]
# alt: create_clock -period 4.000000 [get_pins {f22:Q}]
# GCF Constraint: create_clock -period 76.000000 up_fpga_cs_n_i
# Status: successful
# Translated from net to potential clock up_wr_n_I
# SDC: create_clock -period 76.000000 [get_ports {up_wr_n_I}]
# GCF Constraint: create_clock -period 2.000000 U1/gla_clk_int
# Status: successful
# Translated from net to potential clock U2/Core:GLA
# SDC: create_clock -period 2.000000 [get_pins {U2/Core:GLA}]
# GCF Constraint: create_clock -period 12.000000 adsp_awe_n_i
# Status: failed
# GCF2SDC_E001: cannot find potential clock from net adsp_awe_n_i.
# The constraint cannot be set.
# GCF Constraint: create_clock -period 632.000000 sequencer_rtx_inst/reg_seq_chip_clk_s:Q
# Status: failed
# GCF2SDC_E002: sequencer_rtx_inst/reg_seq_chip_clk_s:Q is not a potential clock.
# The constraint cannot be set.
# GCF Constraint: set_input_to_register_delay 3.000000 -from dat*
# Status: successful
# SDC: set_max_delay 3.000000 -from [get_ports {dat*}] -to [get_clocks {*}]
# GCF Constraint: set_register_to_output_delay 2.000000 -to out
# Status: successful
# SDC: set_max_delay 2.000000 -from [get_clocks {*}] -to [get_ports {out}]
# GCF Constraint: set_max_path_delay 4.000000 s_reg_5.CLK s_reg_5.Q U15.A U15.PAD
# Status: successful
# SDC: set_max_delay 4.000000 -from [get_pins {s_reg_5:CLK}] -to [get_pins {U15:PAD}]
# GCF Constraint: set_false_path -through invIn.Y
# Status: successful
# SDC: set_false_path -through [get_pins {invIn:Y}]
# GCF Constraint: set_multi_cycle_path 3 -from ff1.Q -through invIn.A -to ff2.D
# Warning: The "-through" option is not currently supported in Designer 5.2.
# This constraint is being converted for future compatibility, but the "-through" option will not be honored by Designer 5.2.
# Status: successful
# SDC: set_multicycle_path 3 -from {ff1:CLK} -through {invIn:A} -to {ff2:D}
# GCF Constraint: set_multi_cycle_path 2 -from i2s0/i2sRegs0/i2sConfig[4]
# Status: successful
# SDC: set_multicycle_path 2 -from {i2s0/i2sRegs0/i2sConfig[4]}
# GCF Constraint: set_false_path -from U_ChipMACa/U_MAC/U_DMA/datareq* -through U_SHRAM*/U_ShRAM*
# Warning: The "-from"/"-to" options are not currently supported in Designer 6.0 Production.
# This constraint is being converted for future compatibility, but the "-from"/"-to" options will not be honored by Designer 6.0 Production.
# Status: successful
# SDC: set_false_path -from U_ChipMACa/U_MAC/U_DMA/datareq* -through U_SHRAM*/U_ShRAM*