Libero tools

The Libero Project Manager integrates design tools, streamlines your design flow, manages design and log files, and passes design data between tools.

For more information on Libero tools, please visit: http://www.actel.com/products/tools/overview.html

Project Manager, HDL Editor targets the creation of HDL code. HDL Editor supports VHDL and Verilog with color, high-lighting keywords for both HDL languages.

ViewDraw AE is the Libero schematic entry vehicle.

Synplify AE from Synplicity is integrated as part of the design package, enabling designers to target HDL code to specific Actel devices.

PALACE AE Physical Synthesis from Magma accepts a synthesized netlist and combines logic and architecture-specific optimization with placement-driven mapping based on detailed device and interconnect modeling throughout the physical synthesis process.  The result is a highly optimized design with significant performance improvement without manual intervention, floorplanning, or iterations.

Actel Designer software package includes:

• PinEditor package-level floorplanner and I/O attribute editor

• ChipEditor chip-level module placer

• ChipPlanner displays I/O and logic macros in your design

• NetlistViewer design schematic viewer

• SmartPower power analysis tool

• SmartTime static timing analysis and constraints editor

• SmartGen core generator

ModelSim AE from Mentor Graphics enables source level verification so designers can verify HDL code line by line. Designers can perform simulation at all levels: behavioral (or pre-synthesis), structural (or post-synthesis), and back-annotated, dynamic simulation. (ModelSim is supported in Libero Gold, Platinum, and Platinum Eval only.)

WaveFormer Lite AE from SynaptiCAD allows graphical entering of HDL test benches and manages multiple test benches needed for different design configurations. The graphical test bench generation tool is ideal for designers unfamiliar with the process of creating test benches, or for experts wanting to save time.

Actel Silicon Explorer accelerates device verification. Actel's antifuse FPGAs contain internal probe circuitry that provides built-in, no-cost access to every node in a design, enabling 100% real-time observation and analysis of a device's internal logic without design iteration. The probe circuitry is accessed by Silicon Explorer, an easy to use integrated verification and logic analysis tool that attaches to a PC's standard COM port, turning the PC into a fully functional logic analyzer. Silicon Explorer is also available for download from http://www.actel.com/custsup/updates/siliexp/index.html.